soc: riscv: gd32vf103: simplify MCAUSE exception mask handling

The exception mask needs to cover MCAUSE bits 11:0, there's no need to
overengineer this setting using DT properties.

Ref. https://doc.nucleisys.com/nuclei_spec/isa/core_csr.html#mcause

Signed-off-by: Gerard Marull-Paretas <[email protected]>

Author: gmarull

dts/bindings/cpu/nuclei,bumblebee.yaml

@@ -6,9 +6,3 @@ description: Nuclei Bumblebee RISC-V Core
 compatible: "nuclei,bumblebee"
 
 include: riscv,cpus.yaml
-
-properties:
-  mcause-exception-mask:
-    type: int
-    required: true
-    description: Specify the bits to use for exception code in mcause register.

dts/riscv/gd/gd32vf103.dtsi

@@ -23,7 +23,6 @@
 
 		cpu: cpu@0 {
 			clock-frequency = <DT_FREQ_M(108)>;
-			mcause-exception-mask = <0x7ff>;
 			compatible = "nuclei,bumblebee";
 			riscv,isa = "rv32imac_zicsr_zifencei";
 			reg = <0>;

soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103

@@ -15,7 +15,7 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 27000000
 
 config RISCV_SOC_MCAUSE_EXCEPTION_MASK
-	default $(dt_node_int_prop_hex,/cpus/cpu@0,mcause-exception-mask)
+	default 0xFFF
 
 config RISCV_SOC_INTERRUPT_INIT
 	default y