drivers: clock_control: esp32c2: Add support

Support for ESP32C2 and ESP8684

Signed-off-by: Raffael Rostagno <[email protected]>

Author: Raffael Rostagno

drivers/clock_control/clock_control_esp32.c

@@ -28,11 +28,15 @@
 #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
 #include <esp32s3/rom/rtc.h>
 #include <soc/dport_reg.h>
-#elif CONFIG_SOC_SERIES_ESP32C3
+#elif defined(CONFIG_SOC_SERIES_ESP32C2)
+#define DT_CPU_COMPAT espressif_riscv
+#include <zephyr/dt-bindings/clock/esp32c2_clock.h>
+#include <esp32c2/rom/rtc.h>
+#elif defined(CONFIG_SOC_SERIES_ESP32C3)
 #define DT_CPU_COMPAT espressif_riscv
 #include <zephyr/dt-bindings/clock/esp32c3_clock.h>
 #include <esp32c3/rom/rtc.h>
-#elif CONFIG_SOC_SERIES_ESP32C6
+#elif defined(CONFIG_SOC_SERIES_ESP32C6)
 #define DT_CPU_COMPAT espressif_riscv
 #include <zephyr/dt-bindings/clock/esp32c6_clock.h>
 #include <soc/lp_clkrst_reg.h>
@@ -71,7 +75,7 @@ static bool reset_reason_is_cpu_reset(void)
 
 	if ((rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
 	     rst_reason == RESET_REASON_CPU0_RTC_WDT
-#if !defined(CONFIG_SOC_SERIES_ESP32)
+#if !defined(CONFIG_SOC_SERIES_ESP32) && !defined(CONFIG_SOC_SERIES_ESP32C2)
 	     || rst_reason == RESET_REASON_CPU0_MWDT1
 #endif
 	     )) {
@@ -153,7 +157,9 @@ static void esp32_clock_perip_init(void)
 	 * that have been enabled before reset.
 	 */
 	if (reset_reason_is_cpu_reset()) {
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+	defined(CONFIG_SOC_SERIES_ESP32C3) || \
+	defined(CONFIG_SOC_SERIES_ESP32S3)
 		common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
 		hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
 		wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
@@ -168,7 +174,18 @@ static void esp32_clock_perip_init(void)
 #endif
 	} else {
 		common_perip_clk =
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+			SYSTEM_SPI2_CLK_EN |
+#if ESP_CONSOLE_UART_NUM != 0
+			SYSTEM_UART_CLK_EN |
+#endif
+#if ESP_CONSOLE_UART_NUM != 1
+			SYSTEM_UART1_CLK_EN |
+#endif
+			SYSTEM_LEDC_CLK_EN |
+			SYSTEM_I2C_EXT0_CLK_EN |
+			SYSTEM_LEDC_CLK_EN;
+#elif (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
 			SYSTEM_WDG_CLK_EN |
 			SYSTEM_I2S0_CLK_EN |
 #if ESP_CONSOLE_UART_NUM != 0
@@ -224,7 +241,7 @@ static void esp32_clock_perip_init(void)
 			DPORT_SPI3_DMA_CLK_EN |
 #endif /* CONFIG_SOC_SERIES_ESP32S2 */
 			DPORT_PWM3_CLK_EN;
-#endif /* CONFIG_SOC_SERIES_ESP32C3 || CONFIG_SOC_SERIES_ESP32S3 */
+#endif
 
 #if !defined(CONFIG_SOC_SERIES_ESP32)
 		common_perip_clk1 = 0;
@@ -241,14 +258,22 @@ static void esp32_clock_perip_init(void)
 			DPORT_CRYPTO_SHA_CLK_EN |
 			DPORT_CRYPTO_RSA_CLK_EN;
 #endif /* CONFIG_SOC_SERIES_ESP32S2 */
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+			SYSTEM_CRYPTO_SHA_CLK_EN;
+#endif
 #if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
 			SYSTEM_CRYPTO_AES_CLK_EN |
 			SYSTEM_CRYPTO_SHA_CLK_EN |
 			SYSTEM_CRYPTO_RSA_CLK_EN;
 #endif /* CONFIG_SOC_SERIES_ESP32C3 ||  CONFIG_SOC_SERIES_ESP32S3 */
 
 		wifi_bt_sdio_clk =
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+			SYSTEM_WIFI_CLK_WIFI_EN |
+			SYSTEM_WIFI_CLK_BT_EN_M |
+			SYSTEM_WIFI_CLK_UNUSED_BIT5 |
+			SYSTEM_WIFI_CLK_UNUSED_BIT12;
+#elif (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
 			SYSTEM_WIFI_CLK_WIFI_EN |
 			SYSTEM_WIFI_CLK_BT_EN_M |
 			SYSTEM_WIFI_CLK_I2C_CLK_EN |
@@ -269,7 +294,16 @@ static void esp32_clock_perip_init(void)
 
 	/* Reset peripherals like I2C, SPI, UART, I2S and bring them to known state */
 	common_perip_clk |=
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+			SYSTEM_SPI2_CLK_EN |
+#if ESP_CONSOLE_UART_NUM != 0
+			SYSTEM_UART_CLK_EN |
+#endif
+#if ESP_CONSOLE_UART_NUM != 1
+			SYSTEM_UART1_CLK_EN |
+#endif
+			SYSTEM_I2C_EXT0_CLK_EN;
+#elif (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
 			SYSTEM_I2S0_CLK_EN |
 #if ESP_CONSOLE_UART_NUM != 0
 			SYSTEM_UART_CLK_EN |
@@ -354,7 +388,9 @@ static void esp32_clock_perip_init(void)
 #endif /* CONFIG_SOC_SERIES_ESP32S2 */
 
 	/* Disable some peripheral clocks. */
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+	defined(CONFIG_SOC_SERIES_ESP32C3) || \
+	defined(CONFIG_SOC_SERIES_ESP32S3)
 	CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
 	SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
 
@@ -371,7 +407,9 @@ static void esp32_clock_perip_init(void)
 #endif
 
 	/* Disable hardware crypto clocks. */
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+	defined(CONFIG_SOC_SERIES_ESP32C3) || \
+	defined(CONFIG_SOC_SERIES_ESP32S3)
 	CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
 	SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
 #elif defined(CONFIG_SOC_SERIES_ESP32)
@@ -391,7 +429,9 @@ static void esp32_clock_perip_init(void)
 #endif /* CONFIG_SOC_SERIES_ESP32S3 */
 
 	/* Disable WiFi/BT/SDIO clocks. */
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+	defined(CONFIG_SOC_SERIES_ESP32C3) || \
+	defined(CONFIG_SOC_SERIES_ESP32S3)
 	CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
 	SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
 #else /* CONFIG_SOC_SERIES_ESP32 || CONFIG_SOC_SERIES_ESP32S2 */
@@ -403,7 +443,9 @@ static void esp32_clock_perip_init(void)
 	DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN);
 #endif
 
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+	defined(CONFIG_SOC_SERIES_ESP32C3) || \
+	defined(CONFIG_SOC_SERIES_ESP32S3)
 	/* Set WiFi light sleep clock source to RTC slow clock */
 	REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
 	CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
@@ -418,7 +460,9 @@ static void esp32_clock_perip_init(void)
 	/* Enable RNG clock. */
 	periph_module_enable(PERIPH_RNG_MODULE);
 
-#if (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
+#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
+	defined(CONFIG_SOC_SERIES_ESP32C3) || \
+	defined(CONFIG_SOC_SERIES_ESP32S3)
 	periph_module_enable(PERIPH_TIMG0_MODULE);
 #endif
 }
@@ -494,6 +538,17 @@ static int esp32_select_rtc_slow_clk(uint8_t slow_clk)
 	int retry_32k_xtal = 3;
 
 	do {
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+		if (rtc_slow_clk_src == ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW) {
+			/* external clock needs to be connected to PIN0 before it can
+			 * be used. Here we use rtc_clk_cal function to count
+			 * the number of ext clk cycles in the given number of ext clk
+			 * cycles. If the ext clk has not started up, calibration
+			 * will time out, returning 0.
+			 */
+			LOG_DBG("waiting for external clock by pin0 to start up");
+			rtc_clk_32k_enable_external();
+#else
 		if (rtc_slow_clk_src == ESP32_RTC_SLOW_CLK_SRC_XTAL32K) {
 			/* 32k XTAL oscillator needs to be enabled and running before it can
 			 * be used. Hardware doesn't have a direct way of checking if the
@@ -508,11 +563,17 @@ static int esp32_select_rtc_slow_clk(uint8_t slow_clk)
 			} else if (slow_clk == ESP32_RTC_SLOW_CLK_32K_EXT_OSC) {
 				rtc_clk_32k_enable_external();
 			}
+#endif
 			/* When CONFIG_RTC_CLK_CAL_CYCLES is set to 0, clock calibration will not be
 			 * performed at startup.
 			 */
 			if (CONFIG_RTC_CLK_CAL_CYCLES > 0) {
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+				cal_val = rtc_clk_cal(RTC_CAL_32K_OSC_SLOW,
+								CONFIG_RTC_CLK_CAL_CYCLES);
+#else
 				cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, CONFIG_RTC_CLK_CAL_CYCLES);
+#endif
 				if (cal_val == 0) {
 					if (retry_32k_xtal-- > 0) {
 						continue;
@@ -624,7 +685,7 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf
 	esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * rtc_clk_cfg.cpu_freq_mhz /
 				old_config.freq_mhz);
 
-#if !defined(CONFIG_SOC_SERIES_ESP32C6)
+#if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C6)
 #if ESP_ROM_UART_CLK_IS_XTAL
 	uart_clock_src_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ(1);
 #else

include/zephyr/drivers/clock_control/esp32_clock_control.h

@@ -13,6 +13,8 @@
 #include <zephyr/dt-bindings/clock/esp32s2_clock.h>
 #elif defined(CONFIG_SOC_SERIES_ESP32S3)
 #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
+#elif defined(CONFIG_SOC_SERIES_ESP32C2)
+#include <zephyr/dt-bindings/clock/esp32c2_clock.h>
 #elif defined(CONFIG_SOC_SERIES_ESP32C3)
 #include <zephyr/dt-bindings/clock/esp32c3_clock.h>
 #elif defined(CONFIG_SOC_SERIES_ESP32C6)

include/zephyr/dt-bindings/clock/esp32c2_clock.h

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_
+
+/* Supported CPU clock Sources */
+#define ESP32_CPU_CLK_SRC_XTAL 0U
+#define ESP32_CPU_CLK_SRC_PLL  1U
+#define ESP32_CLK_SRC_RC_FAST  2U
+
+/* Supported CPU frequencies */
+#define ESP32_CLK_CPU_PLL_40M      40000000
+#define ESP32_CLK_CPU_PLL_60M      60000000
+#define ESP32_CLK_CPU_PLL_80M      80000000
+#define ESP32_CLK_CPU_PLL_120M    120000000
+#define ESP32_CLK_CPU_RC_FAST_FREQ  8750000
+
+/* Supported XTAL frequencies */
+#define ESP32_CLK_XTAL_26M 26000000
+#define ESP32_CLK_XTAL_32M 32000000
+#define ESP32_CLK_XTAL_40M 40000000
+
+/* Supported RTC fast clock sources */
+#define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 0
+#define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1
+
+/* Supported RTC slow clock sources */
+#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW      0
+#define ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW     1
+#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2
+
+/* RTC slow clock frequencies */
+#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ      136000
+#define ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW_FREQ      32768
+#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ  68359
+
+/* Modules IDs
+ * These IDs are actually offsets in CLK and RST Control registers.
+ * These IDs shouldn't be changed unless there is a Hardware change
+ * from Espressif.
+ *
+ * Basic Modules
+ * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
+ */
+#define ESP32_LEDC_MODULE               0
+#define ESP32_UART0_MODULE              1
+#define ESP32_UART1_MODULE              2
+#define ESP32_I2C0_MODULE               3
+#define ESP32_TIMG0_MODULE              4
+#define ESP32_TIMG1_MODULE              5  /* No timg1 on esp32c2, TODO: IDF-3825 */
+#define ESP32_UHCI0_MODULE              6
+#define ESP32_SPI_MODULE                7  /* SPI1 */
+#define ESP32_SPI2_MODULE               8  /* SPI2 */
+#define ESP32_RNG_MODULE                9
+#define ESP32_WIFI_MODULE               10
+#define ESP32_BT_MODULE                 11
+#define ESP32_WIFI_BT_COMMON_MODULE     12
+#define ESP32_BT_BASEBAND_MODULE        13
+#define ESP32_BT_LC_MODULE              14
+#define ESP32_AES_MODULE                15
+#define ESP32_SHA_MODULE                16
+#define ESP32_ECC_MODULE                17
+#define ESP32_GDMA_MODULE               18
+#define ESP32_SYSTIMER_MODULE           19
+#define ESP32_SARADC_MODULE             20
+#define ESP32_TEMPSENSOR_MODULE         21
+#define ESP32_MODEM_RPA_MODULE          22
+#define ESP32_MODULE_MAX                23
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_ */

tests/boards/espressif_esp32/rtc_clk/src/rtc_clk_test.c

@@ -15,7 +15,8 @@
 #define DT_CPU_COMPAT espressif_xtensa_lx6
 #elif defined(CONFIG_SOC_SERIES_ESP32S2) || defined(CONFIG_SOC_SERIES_ESP32S3)
 #define DT_CPU_COMPAT espressif_xtensa_lx7
-#elif defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
+#elif defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3) || \
+	defined(CONFIG_SOC_SERIES_ESP32C6)
 #define DT_CPU_COMPAT espressif_riscv
 #endif
 
@@ -74,8 +75,13 @@ ZTEST(rtc_clk, test_cpu_xtal_src)
 
 uint32_t rtc_pll_src_freq_mhz[] = {
 	ESP32_CLK_CPU_PLL_80M,
+#if defined(CONFIG_SOC_SERIES_ESP32C2)
+	ESP32_CLK_CPU_PLL_120M,
+#else
 	ESP32_CLK_CPU_PLL_160M,
-#if !defined(CONFIG_SOC_SERIES_ESP32C3) && !defined(CONFIG_SOC_SERIES_ESP32C6)
+#endif
+#if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C3) && \
+	!defined(CONFIG_SOC_SERIES_ESP32C6)
 	ESP32_CLK_CPU_PLL_240M,
 #endif
 };