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nashifMaureenHelm
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soc: mec1501: add timing support
Use custom timing implementation specific for this SoC. Signed-off-by: Anas Nashif <[email protected]>
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soc/arm/microchip_mec/mec1501/CMakeLists.txt

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@@ -12,3 +12,12 @@ zephyr_sources_ifdef(CONFIG_SYS_POWER_MANAGEMENT
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device_power.c
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power.c
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)
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if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS)
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if(CONFIG_TIMING_FUNCTIONS)
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# Use MEC15xx timing calculations only if DWT is not present
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if(NOT CONFIG_CORTEX_M_DWT)
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zephyr_library_sources(timing.c)
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endif()
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endif()
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endif()

soc/arm/microchip_mec/mec1501/Kconfig.defconfig.series

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@@ -21,6 +21,9 @@ if RTOS_TIMER
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config MCHP_XEC_RTOS_TIMER
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default y
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config SOC_HAS_TIMING_FUNCTIONS
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default y
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config ARCH_HAS_CUSTOM_BUSY_WAIT
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default y
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/*
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* Copyright (c) 2020 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/arm/aarch32/arch.h>
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#include <kernel.h>
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#include <sys_clock.h>
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#include <timing/timing.h>
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#include <soc.h>
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void timing_init(void)
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{
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/* Setup counter */
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B32TMR1_REGS->CTRL = MCHP_BTMR_CTRL_ENABLE |
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MCHP_BTMR_CTRL_AUTO_RESTART |
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MCHP_BTMR_CTRL_COUNT_UP;
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B32TMR1_REGS->PRLD = 0; /* Preload */
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B32TMR1_REGS->CNT = 0; /* Counter value */
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B32TMR1_REGS->IEN = 0; /* Disable interrupt */
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B32TMR1_REGS->STS = 1; /* Clear interrupt */
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}
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void timing_start(void)
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{
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B32TMR1_REGS->CTRL |= MCHP_BTMR_CTRL_START;
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}
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void timing_stop(void)
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{
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B32TMR1_REGS->CTRL &= ~MCHP_BTMR_CTRL_START;
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}
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timing_t timing_counter_get(void)
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{
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return B32TMR1_REGS->CNT;
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}
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uint64_t timing_cycles_get(volatile timing_t *const start,
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volatile timing_t *const end)
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{
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return (*end - *start);
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}
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uint64_t timing_freq_get(void)
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{
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return CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
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}
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uint64_t timing_cycles_to_ns(uint64_t cycles)
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{
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return (cycles) * (NSEC_PER_SEC) / (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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}
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uint64_t timing_cycles_to_ns_avg(uint64_t cycles, uint32_t count)
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{
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return (uint32_t)timing_cycles_to_ns(cycles) / count;
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}
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uint32_t timing_freq_get_mhz(void)
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{
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return (uint32_t)(timing_freq_get() / 1000000);
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}

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