drivers: i3c: dw: enhance open-drain timing configuration

This commit improves the I3C handling of open-drain
timing configurations with the following changes:
- Add OD minimum high_ns and low_ns DT properties
- Implement dw_i3c_init_scl_timing for runtime timing updates
- Initialize scl_od_min configuration from device tree
- Maintain backward compatibility with existing configurations

Requirement (MIPI Specification for I3C Basic v1.2 (16-Dec-2024),
             Section 4.3.11.2 & Table 49):
- The MIPI I3C specification mandates different open-drain speeds during
  bus initialization as defined in
  "I3C Basic Open Drain Timing Parameters".
- The first broadcast address (7'h7E+W) must be transmitted at a slower
  open-drain speed to ensure visibility to all devices on the I3C bus,
  including legacy I2C devices. This slow speed (minimum 200ns Thigh)
  allows I2C devices to properly detect the I3C mode transition and
  disable their spike filters before switching to I3C mode. After the
  initial broadcast, normal I3C open-drain speeds can be used for
  regular operation.

Signed-off-by: Shreehari HK <[email protected]>

Author: Shreehari-AlifSemi

drivers/i3c/i3c_dw.c

@@ -365,12 +365,6 @@ struct dw_i3c_config {
 	clock_control_subsys_t clock_subsys;
 	uint32_t regs;
 
-	/* Initial clk configuration */
-	/* Maximum OD high clk pulse length */
-	uint32_t od_thigh_max_ns;
-	/* Minimum OD low clk pulse length */
-	uint32_t od_tlow_min_ns;
-
 	void (*irq_config_func)();
 
 #if defined(CONFIG_PINCTRL)
@@ -1414,7 +1408,7 @@ static int i3c_dw_irq(const struct device *dev)
 	return 0;
 }
 
-static int init_scl_timing(const struct device *dev)
+static int dw_i3c_init_scl_timing(const struct device *dev, struct i3c_config_controller *ctrl_cfg)
 {
 	const struct dw_i3c_config *config = dev->config;
 	uint32_t core_rate, scl_timing;
@@ -1427,12 +1421,21 @@ static int init_scl_timing(const struct device *dev)
 		LOG_ERR("%s: get clock rate failed", dev->name);
 		return -EINVAL;
 	}
+
 #ifdef CONFIG_I3C_CONTROLLER
+
+	__ASSERT((ctrl_cfg != NULL), "Controller configuration should not be NULL");
+
+	if (ctrl_cfg->scl_od_min.low_ns < I3C_OD_TLOW_MIN_NS) {
+		LOG_ERR("%s: Open Drain Low Period is out of range", dev->name);
+		return -EINVAL;
+	}
+
 	/* I3C_OD */
-	hcnt = DIV_ROUND_UP(config->od_thigh_max_ns * (uint64_t)core_rate, I3C_PERIOD_NS) - 1;
+	hcnt = DIV_ROUND_UP(ctrl_cfg->scl_od_min.high_ns * (uint64_t)core_rate, I3C_PERIOD_NS) - 1;
 	hcnt = CLAMP(hcnt, SCL_I3C_TIMING_CNT_MIN, SCL_I3C_TIMING_CNT_MAX);
 
-	lcnt = DIV_ROUND_UP(config->od_tlow_min_ns * (uint64_t)core_rate, I3C_PERIOD_NS);
+	lcnt = DIV_ROUND_UP(ctrl_cfg->scl_od_min.low_ns * (uint64_t)core_rate, I3C_PERIOD_NS);
 	lcnt = CLAMP(lcnt, SCL_I3C_TIMING_CNT_MIN, SCL_I3C_TIMING_CNT_MAX);
 
 	scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
@@ -1491,8 +1494,10 @@ static int init_scl_timing(const struct device *dev)
 		DIV_ROUND_UP(I3C_BUS_IDLE_TIME_NS * (uint64_t)core_rate, I3C_PERIOD_NS);
 	sys_write32(BUS_I3C_IDLE_TIME(scl_timing), config->regs + BUS_IDLE_TIMING);
 #endif /* CONFIG_I3C_TARGET */
+
 	return 0;
 }
+
 #ifdef CONFIG_I3C_CONTROLLER
 /**
  * Determine I3C bus mode from the i2c devices on the bus
@@ -1634,6 +1639,7 @@ static int set_controller_info(const struct device *dev)
 	return 0;
 }
 #endif /* CONFIG_I3C_CONTROLLER */
+
 static void enable_interrupts(const struct device *dev)
 {
 	const struct dw_i3c_config *config = dev->config;
@@ -2072,17 +2078,28 @@ static int dw_i3c_config_get(const struct device *dev, enum i3c_config_type type
  */
 static int dw_i3c_configure(const struct device *dev, enum i3c_config_type type, void *config)
 {
+#ifdef CONFIG_I3C_CONTROLLER
+	struct dw_i3c_data *data = dev->data;
+	int ret;
+#endif /* CONFIG_I3C_CONTROLLER */
 #ifdef CONFIG_I3C_TARGET
 	const struct dw_i3c_config *dev_config = dev->config;
 #endif /* CONFIG_I3C_TARGET */
 
 	if (type == I3C_CONFIG_CONTROLLER) {
-		/* struct i3c_config_controller *ctrl_cfg = config; */
-		/* TODO: somehow determine i3c rate? snps is complicated */
+#ifdef CONFIG_I3C_CONTROLLER
+		ret = dw_i3c_init_scl_timing(dev, config);
+		if (ret != 0) {
+			return ret;
+		}
+		(void)memcpy(&data->common.ctrl_config,
+			     config, sizeof(data->common.ctrl_config));
+#else
 		return -ENOTSUP;
+#endif /* CONFIG_I3C_CONTROLLER */
 	} else if (type == I3C_CONFIG_TARGET) {
 #ifdef CONFIG_I3C_TARGET
-		struct i3c_config_target *target_cfg = config;
+		struct i3c_config_target *target_cfg = (struct i3c_config_target *)config;
 		uint32_t val;
 
 		/* TODO: some how randomly generate pid */
@@ -2357,13 +2374,6 @@ static int dw_i3c_init(const struct device *dev)
 	__ASSERT_NO_MSG((IS_ENABLED(CONFIG_I3C_TARGET) && ctrl_config->is_secondary) ||
 			(IS_ENABLED(CONFIG_I3C_CONTROLLER) && !ctrl_config->is_secondary));
 
-	ret = init_scl_timing(dev);
-	if (ret != 0) {
-		return ret;
-	}
-
-	enable_interrupts(dev);
-
 	/* disable ibi */
 	sys_write32(IBI_REQ_REJECT_ALL, config->regs + IBI_SIR_REQ_REJECT);
 	sys_write32(IBI_REQ_REJECT_ALL, config->regs + IBI_MR_REQ_REJECT);
@@ -2385,6 +2395,15 @@ static int dw_i3c_init(const struct device *dev)
 	}
 #endif /* CONFIG_I3C_CONTROLLER */
 	dw_i3c_enable_controller(config, true);
+
+	ret = dw_i3c_init_scl_timing(dev, ctrl_config);
+	if (ret != 0) {
+		LOG_ERR("%s: Clock setting failed", dev->name);
+		return ret;
+	}
+
+	enable_interrupts(dev);
+
 #ifdef CONFIG_I3C_CONTROLLER
 	if (!(ctrl_config->is_secondary)) {
 		/* Perform bus initialization - skip if no I3C devices are known. */
@@ -2497,15 +2516,15 @@ static DEVICE_API(i3c, dw_i3c_api) = {
 		.common.ctrl_config.scl.i3c =                                                      \
 			DT_INST_PROP_OR(n, i3c_scl_hz, I3C_BUS_TYP_I3C_SCL_RATE),                  \
 		.common.ctrl_config.scl.i2c = DT_INST_PROP_OR(n, i2c_scl_hz, 0),                   \
+		.common.ctrl_config.scl_od_min.high_ns = DT_INST_PROP(n, od_thigh_min_ns),         \
+		.common.ctrl_config.scl_od_min.low_ns = DT_INST_PROP(n, od_tlow_min_ns),           \
 	};                                                                                         \
 	static const struct dw_i3c_config dw_i3c_cfg_##n = {                                       \
 		.regs = DT_INST_REG_ADDR(n),                                                       \
 		.clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),                                    \
 		.clock_subsys = COND_CODE_1(DT_INST_PHA_HAS_CELL(n, clocks, clkid),                \
 				((clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, clkid)),           \
 				((clock_control_subsys_t)0)),                                      \
-		.od_thigh_max_ns = DT_INST_PROP(n, od_thigh_max_ns),                               \
-		.od_tlow_min_ns = DT_INST_PROP(n, od_tlow_min_ns),                                 \
 		.irq_config_func = &i3c_dw_irq_config_##n,                                         \
 		IF_ENABLED(CONFIG_I3C_CONTROLLER,                                                  \
 			(.common.dev_list.i3c = dw_i3c_device_array_##n,                           \

dts/bindings/i3c/i3c-controller.yaml

@@ -38,3 +38,20 @@ properties:
       is the address is used to communicate with itself after a handoff by
       a secondary controller. This is only used if the controller is a primary
       controller.
+
+  od-thigh-min-ns:
+    type: int
+    default: 24
+    description: |
+      Minimum high clock pulse length (ns) in Open-Drain mode for pure bus.
+      The default value is from Section 4.3.11.2 & Table 49 of the I3C
+      Basic Specifiction v1.2 (16-Dec-2024).
+
+  od-tlow-min-ns:
+    type: int
+    default: 200
+    description: |
+      Minimum low clock pulse length (ns) in Open-Drain mode.
+      The default value is from Section 4.3.11.2 & Table 49 of the I3C
+      Basic Specifiction v1.2 (16-Dec-2024).
+      Specifiction.

dts/bindings/i3c/snps,designware-i3c.yaml

@@ -12,19 +12,3 @@ include: [i3c-controller.yaml, pinctrl-device.yaml]
 properties:
   clocks:
     required: true
-
-  od-thigh-max-ns:
-    type: int
-    default: 41
-    description: |
-      Maximum high clock pulse length (ns) in Open-Drain mode.
-      The default is value from Section 6.2 of the I3C
-      Specifiction.
-
-  od-tlow-min-ns:
-    type: int
-    default: 200
-    description: |
-      Minimum low clock pulse length (ns) in Open-Drain mode.
-      The default is value from Section 6.2 of the I3C
-      Specifiction.