Skip to content

Commit 52b397e

Browse files
finikorgfabiobaltieri
finikorg
authored and
fabiobaltieri
committed
boards: Add Alder Lake board definition
Add initial Alder Lake board definition. Initially copied from ELkhart Lake which is predecessor of the board. Signed-off-by: Andrei Emeltchenko <[email protected]>
1 parent c6e322d commit 52b397e

File tree

12 files changed

+293
-0
lines changed

12 files changed

+293
-0
lines changed

‎boards/x86/intel_adl/CMakeLists.txt‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
# Create an EFI image
2+
if((CONFIG_BOARD_INTEL_ADL_CRB OR CONFIG_BOARD_INTEL_ADL_RVP) AND CONFIG_BUILD_OUTPUT_EFI)
3+
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
4+
COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py
5+
-c ${CMAKE_C_COMPILER}
6+
-o ${CMAKE_OBJCOPY}
7+
-i ${ZEPHYR_BASE}/include
8+
-f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf
9+
$<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
10+
WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
11+
)
12+
endif()

‎boards/x86/intel_adl/Kconfig.board‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
# Copyright (c) 2023 Intel Corporation
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
config BOARD_INTEL_ADL_CRB
5+
bool "Alder Lake CRB"
6+
depends on SOC_ALDER_LAKE
7+
select X86_64
8+
select HAS_COVERAGE_SUPPORT
9+
10+
config BOARD_INTEL_ADL_RVP
11+
bool "Alder Lake RVP"
12+
depends on SOC_ALDER_LAKE
13+
select X86_64
14+
select HAS_COVERAGE_SUPPORT

‎boards/x86/intel_adl/Kconfig.defconfig‎

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
# Copyright (c) 2023 Intel Corporation
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
if BOARD_INTEL_ADL_CRB || BOARD_INTEL_ADL_RVP
5+
6+
config BOARD
7+
default "intel_adl_crb" if BOARD_INTEL_ADL_CRB
8+
default "intel_adl_rvp" if BOARD_INTEL_ADL_RVP
9+
10+
config BUILD_OUTPUT_STRIPPED
11+
default y
12+
13+
config MP_MAX_NUM_CPUS
14+
default 2
15+
16+
# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
17+
config SYS_CLOCK_HW_CYCLES_PER_SEC
18+
default 1900000000 if APIC_TSC_DEADLINE_TIMER
19+
default 1900000000 if APIC_TIMER_TSC
20+
default 19200000
21+
22+
if APIC_TIMER
23+
config APIC_TIMER_IRQ
24+
default 24
25+
config APIC_TIMER_TSC_M
26+
default 3
27+
config APIC_TIMER_TSC_N
28+
default 249
29+
endif
30+
31+
config ACPI
32+
default y
33+
34+
endif # BOARD_INTEL_ADL_CRB || BOARD_INTEL_ADL_RVP
35+
36+
if BOARD_INTEL_ADL_RVP
37+
38+
config UART_NS16550_ACCESS_IOPORT
39+
default y if UART_NS16550
40+
41+
endif # BOARD_INTEL_ADL_RVP

‎boards/x86/intel_adl/board.cmake‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
# SPDX-License-Identifier: Apache-2.0
2+
3+
board_set_flasher_ifnset(misc-flasher)
4+
board_finalize_runner_args(misc-flasher)

‎boards/x86/intel_adl/doc/index.rst‎

Lines changed: 108 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,108 @@
1+
.. _intel_adl_crb:
2+
3+
Alder Lake CRB
4+
##############
5+
6+
Overview
7+
********
8+
Alder Lake Reference Board (INTEL_ADL CRB) is an example implementation of a
9+
compact single board computer with high performance for IoT edge devices.
10+
11+
This board configuration enables kernel support for the `INTEL_ADL`_ board.
12+
13+
Hardware
14+
********
15+
16+
General information about the board can be found at the `INTEL_ADL`_ website.
17+
18+
Connections and IOs
19+
===================
20+
21+
Refer to the `INTEL_ADL`_ website for more information.
22+
23+
Programming and Debugging
24+
*************************
25+
Use the following procedures for booting an image on a RPL CRB board.
26+
27+
.. contents::
28+
:depth: 1
29+
:local:
30+
:backlinks: top
31+
32+
Build Zephyr application
33+
========================
34+
35+
#. Build a Zephyr application; for instance, to build the ``hello_world``
36+
application on Alder Lake CRB:
37+
38+
.. zephyr-app-commands::
39+
:zephyr-app: samples/hello_world
40+
:board: intel_adl_crb
41+
:goals: build
42+
43+
.. note::
44+
45+
A Zephyr EFI image file named :file:`zephyr.efi` is automatically
46+
created in the build directory after the application is built.
47+
48+
Preparing the Boot Device
49+
=========================
50+
51+
Prepare a USB flash drive to boot the Zephyr application image on
52+
an Alder Lake CRB board.
53+
54+
#. Format the USB flash drive as FAT32.
55+
56+
On Windows, open ``File Explorer``, and right-click on the USB flash drive.
57+
Select ``Format...``. Make sure in ``File System``, ``FAT32`` is selected.
58+
Click on the ``Format`` button and wait for it to finish.
59+
60+
On Linux, graphical utilities such as ``gparted`` can be used to format
61+
the USB flash drive as FAT32. Alternatively, under terminal, find out
62+
the corresponding device node for the USB flash drive (for example,
63+
``/dev/sdd``). Execute the following command:
64+
65+
.. code-block:: console
66+
67+
$ mkfs.vfat -F 32 <device-node>
68+
69+
.. important::
70+
Make sure the device node is the actual device node for
71+
the USB flash drive. Or else you may erase other storage devices
72+
on your system, and will render the system unusable afterwards.
73+
74+
#. Copy the Zephyr EFI image file :file:`zephyr/zephyr.efi` to the USB drive.
75+
76+
Booting the Alder Lake CRB Board
77+
================================
78+
79+
Boot the Alder Lake CRB board to the EFI shell with USB flash drive connected.
80+
81+
#. Insert the prepared boot device (USB flash drive) into the Alder Lake CRB board.
82+
83+
#. Connect the board to the host system using the serial cable and
84+
configure your host system to watch for serial data. See
85+
`INTEL_ADL`_ website for more information.
86+
87+
.. note::
88+
On Windows, PuTTY has an option to set up configuration for
89+
serial data. Use a baud rate of 115200.
90+
91+
#. Power on the Alder Lake CRB board.
92+
93+
#. When the following output appears, press :kbd:`F7`:
94+
95+
.. code-block:: console
96+
97+
Press <DEL> or <ESC> to enter setup.
98+
99+
#. From the menu that appears, select the menu entry that describes
100+
that particular EFI shell.
101+
102+
#. From the EFI shell select Zephyr EFI image to boot.
103+
104+
.. code-block:: console
105+
106+
Shell> fs0:zephyr.efi
107+
108+
.. _INTEL_ADL: https://ark.intel.com/content/www/us/en/ark/products/codename/232598/products-formerly-alder-laken.html

‎boards/x86/intel_adl/intel_adl.dts‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
/*
2+
* Copyright (c) 2023 Intel Corporation
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/dts-v1/;
8+
9+
#include <mem.h>
10+
11+
#define DT_DRAM_SIZE DT_SIZE_M(2048)
12+
13+
#include <intel/alder_lake.dtsi>
14+
15+
/ {
16+
model = "Alder Lake";
17+
compatible = "intel,alder_lake";
18+
19+
chosen {
20+
zephyr,sram = &dram0;
21+
};
22+
};

‎boards/x86/intel_adl/intel_adl_crb.dts‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
/*
2+
* Copyright (c) 2023 Intel Corporation
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include "intel_adl.dts"
8+
9+
/ {
10+
chosen {
11+
zephyr,console = &uart0;
12+
zephyr,shell-uart = &uart0;
13+
};
14+
};

‎boards/x86/intel_adl/intel_adl_crb.yaml‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
identifier: intel_adl_crb
2+
name: Alder Lake CRB
3+
type: mcu
4+
arch: x86
5+
toolchain:
6+
- zephyr
7+
ram: 2048
8+
testing:
9+
timeout_multiplier: 4
10+
ignore_tags:
11+
- net
12+
- bluetooth

‎boards/x86/intel_adl/intel_adl_crb_defconfig‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
# SPDX-License-Identifier: Apache-2.0
2+
3+
CONFIG_SOC_ALDER_LAKE=y
4+
CONFIG_BOARD_INTEL_ADL_CRB=y
5+
CONFIG_PIC_DISABLE=y
6+
CONFIG_LOAPIC=y
7+
CONFIG_CONSOLE=y
8+
CONFIG_SERIAL=y
9+
CONFIG_UART_NS16550=y
10+
CONFIG_UART_CONSOLE=y
11+
CONFIG_X2APIC=y
12+
CONFIG_SMP=y
13+
CONFIG_BUILD_OUTPUT_EFI=y
14+
CONFIG_BUILD_NO_GAP_FILL=y
15+
CONFIG_HEAP_MEM_POOL_SIZE=64000000
16+
CONFIG_MAIN_STACK_SIZE=320000
17+
CONFIG_UART_NS16550_PARENT_INIT_LEVEL=y
18+
CONFIG_SHELL_BACKEND_SERIAL_INIT_PRIORITY=55

‎boards/x86/intel_adl/intel_adl_rvp.dts‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
/*
2+
* Copyright (c) 2023 Intel Corporation
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include "intel_adl.dts"
8+
9+
/ {
10+
chosen {
11+
zephyr,console = &uart0_legacy;
12+
zephyr,shell-uart = &uart0_legacy;
13+
};
14+
};
15+
16+
&uart0 {
17+
status = "disabled";
18+
};

0 commit comments

Comments
 (0)