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soc: alder_lake: Add Adler Lake SoC
Add Adler Lake SoC. The SoC is derived from Elkhart Lake SoC. Signed-off-by: Andrei Emeltchenko <[email protected]>
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‎dts/bindings/cpu/intel,alder_lake.yaml‎

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# Copyright (c) 2023 Intel Corp.
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# SPDX-License-Identifier: Apache-2.0
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description: Intel Alder Lake CPU
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compatible: "intel,alder-lake"
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include: cpu.yaml

‎dts/x86/intel/alder_lake.dtsi‎

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/*
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* Copyright (c) 2023 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pcie/pcie.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,alder_lake";
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d-cache-line-size = <64>;
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reg = <0>;
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};
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};
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dram0: memory@0 {
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device_type = "memory";
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reg = <0x0 DT_DRAM_SIZE>;
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};
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intc: ioapic@fec00000 {
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compatible = "intel,ioapic";
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reg = <0xfec00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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pcie0: pcie0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "intel,pcie";
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ranges;
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smbus0: smbus0 {
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compatible = "intel,pch-smbus";
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#address-cells = <1>;
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#size-cells = <0>;
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vendor-id = <0x8086>;
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device-id = <0x54a3>;
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interrupts = <16 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "okay";
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};
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uart0: uart0 {
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compatible = "ns16550";
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vendor-id = <0x8086>;
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device-id = <0x54a8>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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reg-shift = <2>;
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interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
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interrupt-parent = <&intc>;
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status = "okay";
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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uart0_legacy: uart@3f8 {
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compatible = "ns16550";
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reg = <0x000003f8 0x100>;
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clock-frequency = <1843200>;
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interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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reg-shift = <0>;
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status = "okay";
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};
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hpet: hpet@fed00000 {
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compatible = "intel,hpet";
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reg = <0xfed00000 0x400>;
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interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
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interrupt-parent = <&intc>;
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status = "okay";
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};
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counter: counter@70 {
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compatible = "motorola,mc146818";
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reg = <0x70 0x0D 0x71 0x0D>;
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status = "okay";
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};
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tco_wdt: tco_wdt@400 {
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compatible = "intel,tco-wdt";
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reg = <0x0400 0x20>;
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};
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};
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};

‎soc/x86/alder_lake/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
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zephyr_cc_option(-march=goldmont)
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zephyr_library_sources(cpu.c)

‎soc/x86/alder_lake/Kconfig.defconfig‎

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# Alder Lake SoC configuration options
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# Copyright (c) 2018-2023 Intel Corporation
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_ALDER_LAKE
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config SOC
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default "alder_lake"
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config PCIE_MMIO_CFG
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default y
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config X86_DYNAMIC_IRQ_STUBS
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default 16
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depends on DYNAMIC_INTERRUPTS
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endif # SOC_ALDER_LAKE

‎soc/x86/alder_lake/Kconfig.soc‎

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# Copyright (c) 2018-2023 Intel Corporation Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_ALDER_LAKE
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bool "Intel Alder Lake SOC"
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select X86
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select CPU_ATOM
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select PCIE
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select PCIE_MSI
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select DYNAMIC_INTERRUPTS
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select X86_MMU

‎soc/x86/alder_lake/cpu.c‎

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/*
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* Copyright (c) 2023 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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uint8_t x86_cpu_loapics[] = { 0x00, 0x02, 0x04, 0x06 };

‎soc/x86/alder_lake/doc/supported_features.txt‎

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Supported Features
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==================
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In addition to the standard architecture devices (HPET, local and I/O APICs,
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etc.), Zephyr supports the following Alder Lake-specific SoC devices:
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* I2C
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* SMBus
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UART Serial Port Support
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-------------------------------------
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The Alder Lake UARTs are NS16550-compatible. Baud rate of
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115.2kbps is supported.

‎soc/x86/alder_lake/linker.ld‎

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/*
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* Copyright (c) 2011-2014, Wind River Systems, Inc.
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* Copyright (c) 2019-2023 Intel Corp.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/x86/memory.ld>
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#ifdef CONFIG_X86_64
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#include <zephyr/arch/x86/intel64/linker.ld>
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#else
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#include <zephyr/arch/x86/ia32/linker.ld>
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#endif /* CONFIG_X86_64 */

‎soc/x86/alder_lake/soc.h‎

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/*
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* Copyright (c) 2018-2023, Intel Corporation
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* Copyright (c) 2010-2015, Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Board configuration macros for the Alder Lake SoC
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*
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* This header file is used to specify and describe soc-level aspects for
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* the 'Alder Lake' SoC.
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*/
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#ifndef __SOC_H_
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#define __SOC_H_
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#include <zephyr/sys/util.h>
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#ifndef _ASMLANGUAGE
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#include <zephyr/device.h>
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#include <zephyr/random/rand32.h>
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#endif
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#ifdef CONFIG_GPIO_INTEL
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#include "soc_gpio.h"
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#endif
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#if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie)
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#include <zephyr/drivers/pcie/pcie.h>
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#define X86_SOC_EARLY_SERIAL_PCIDEV PCIE_BDF(0, 0x19, 2) /* uart2 */
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#else
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#define X86_SOC_EARLY_SERIAL_MMIO8_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_console))
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#endif
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#endif /* __SOC_H_ */

‎soc/x86/alder_lake/soc_gpio.h‎

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/*
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* Copyright (c) 2021-2023, Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief GPIO macros for the Alder Lake SoC
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*
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* This header file is used to specify the GPIO macros for
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* the Alder Lake SoC.
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*/
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#ifndef __SOC_GPIO_H_
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#define __SOC_GPIO_H_
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#define GPIO_INTEL_NR_SUBDEVS 15
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#define REG_PAD_OWNER_BASE 0x0020
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#define REG_GPI_INT_STS_BASE 0x0100
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#define PAD_CFG0_PMODE_MASK (0x0F << 10)
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#define REG_PAD_BASE_ADDR 0x000C
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#define REG_GPI_INT_EN_BASE 0x0120
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#define REG_PAD_HOST_SW_OWNER 0x0B0
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#define PAD_BASE_ADDR_MASK 0xfff
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#define GPIO_REG_BASE(reg_base) \
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(reg_base & ~PAD_BASE_ADDR_MASK)
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#define GPIO_PAD_BASE(reg_base) \
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(reg_base & PAD_BASE_ADDR_MASK)
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#define GPIO_PAD_OWNERSHIP(raw_pin, pin_offset) \
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(pin_offset % 8) ? \
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REG_PAD_OWNER_BASE + \
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((((pin_offset / 8) + 1) + (raw_pin / 8)) * 0x4) : \
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REG_PAD_OWNER_BASE + \
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(((pin_offset / 8) + (raw_pin / 8)) * 0x4); \
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#define GPIO_OWNERSHIP_BIT(raw_pin) ((raw_pin % 8) * 4)
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#define GPIO_RAW_PIN(pin, pin_offset) pin
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#define GPIO_INTERRUPT_BASE(cfg) \
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(cfg->group_index * 0x4)
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#define GPIO_BASE(cfg) \
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(cfg->group_index * 0x4)
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#define PIN_OFFSET 0x10
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#endif /* __SOC_GPIO_H_ */

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