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soc: atmel_sam0: Add support for SAML21 parts
Implement support for SAML21 parts, tested on a SAML21 Xplained Pro dev board. Confirmed operational peripherals: UART, GPIO, PWM, ADC. Signed-off-by: Attie Grande <[email protected]>
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‎dts/arm/atmel/saml21.dtsi‎

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/*
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* Copyright (c) 2021 Argentum Systems Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <atmel/saml2x.dtsi>
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/ {
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soc {
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usb0: usb@41000000 {
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compatible = "atmel,sam0-usb";
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status = "disabled";
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reg = <0x41000000 0x1000>;
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interrupts = <6 0>;
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num-bidir-endpoints = <8>;
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label = "USB0";
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};
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dmac: dmac@44000400 {
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compatible = "atmel,sam0-dmac";
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reg = <0x44000400 0x50>;
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interrupts = <5 0>;
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label = "DMA_0";
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#dma-cells = <2>;
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};
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tcc0: tcc@42001400 {
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compatible = "atmel,sam0-tcc";
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reg = <0x42001400 0x80>;
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interrupts = <14 0>;
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label = "TCC_0";
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clocks = <&gclk 25>, <&mclk 0x1c 5>;
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clock-names = "GCLK", "MCLK";
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channels = <4>;
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counter-size = <24>;
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};
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tcc1: tcc@42001800 {
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compatible = "atmel,sam0-tcc";
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reg = <0x42001800 0x80>;
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interrupts = <15 0>;
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label = "TCC_1";
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clocks = <&gclk 25>, <&mclk 0x1c 6>;
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clock-names = "GCLK", "MCLK";
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channels = <4>;
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counter-size = <24>;
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};
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tcc2: tcc@42001c00 {
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compatible = "atmel,sam0-tcc";
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reg = <0x42001C00 0x80>;
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interrupts = <16 0>;
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label = "TCC_2";
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clocks = <&gclk 26>, <&mclk 0x1c 7>;
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clock-names = "GCLK", "MCLK";
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channels = <2>;
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counter-size = <16>;
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};
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};
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};
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&dac {
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interrupts = <24 0>;
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clocks = <&gclk 32>, <&mclk 0x1c 12>;
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clock-names = "GCLK", "MCLK";
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};
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&sercom0 {
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interrupts = <8 0>;
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clocks = <&gclk 18>, <&mclk 0x1c 0>;
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clock-names = "GCLK", "MCLK";
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};
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&sercom1 {
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interrupts = <9 0>;
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clocks = <&gclk 19>, <&mclk 0x1c 1>;
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clock-names = "GCLK", "MCLK";
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};
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&sercom2 {
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interrupts = <10 0>;
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clocks = <&gclk 20>, <&mclk 0x1c 2>;
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clock-names = "GCLK", "MCLK";
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};
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&sercom3 {
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interrupts = <11 0>;
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clocks = <&gclk 21>, <&mclk 0x1c 3>;
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clock-names = "GCLK", "MCLK";
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};
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&sercom4 {
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interrupts = <12 0>;
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clocks = <&gclk 22>, <&mclk 0x1c 4>;
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clock-names = "GCLK", "MCLK";
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};
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&sercom5 {
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interrupts = <13 0>;
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clocks = <&gclk 24>, <&mclk 0x20 1>;
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clock-names = "GCLK", "MCLK";
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};
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&tc4 {
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interrupts = <21 0>;
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clocks = <&gclk 29>, <&mclk 0x20 2>;
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clock-names = "GCLK", "MCLK";
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};
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&adc {
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interrupts = <22 0>;
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interrupt-names = "resrdy";
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clocks = <&gclk 30>, <&mclk 0x20 3>;
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clock-names = "GCLK", "MCLK";
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};

‎dts/arm/atmel/saml2x.dtsi‎

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/*
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* Copyright (c) 2021 Argentum Systems Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv6-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/pwm/pwm.h>
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/ {
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aliases {
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watchdog0 = &wdog;
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};
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chosen {
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zephyr,flash-controller = &nvmctrl;
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zephyr,entropy = &trng;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m0+";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 0x8000>;
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};
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id: device_id@80a00c {
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compatible = "atmel,sam0-id";
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reg = <0x0080A00C 0x4>,
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<0x0080A040 0x4>,
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<0x0080A044 0x4>,
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<0x0080A048 0x4>;
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};
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soc {
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nvmctrl: nvmctrl@41004000 {
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compatible = "atmel,sam0-nvmctrl";
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label = "FLASH_CTRL";
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reg = <0x41004000 0x22>;
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interrupts = <4 0>;
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lock-regions = <16>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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label = "FLASH_0";
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reg = <0 0x40000>;
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write-block-size = <4>;
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};
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};
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pm: pm@40000400 {
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compatible = "atmel,saml2x-pm";
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reg = <0x40000400 0x400>;
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interrupts = <0 0>;
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#clock-cells = <2>;
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};
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mclk: mclk@40000400 {
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compatible = "atmel,saml2x-mclk";
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reg = <0x40000400 0x400>;
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#clock-cells = <2>;
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};
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gclk: gclk@40001800 {
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compatible = "atmel,saml2x-gclk";
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reg = <0x40001800 0x400>;
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#clock-cells = <1>;
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};
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dmac: dmac@44000400 {
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compatible = "atmel,sam0-dmac";
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reg = <0x44000400 0x400>;
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interrupts = <5 0>;
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label = "DMA_0";
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#dma-cells = <2>;
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};
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eic: eic@40002400 {
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compatible = "atmel,sam0-eic";
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reg = <0x40002400 0x24>;
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interrupts = <3 0>;
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label = "EIC";
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};
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wdog: watchdog@40001c00 {
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compatible = "atmel,sam0-watchdog";
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reg = <0x40001c00 0x0c>;
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interrupts = <1 0>;
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label = "WATCHDOG_0";
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};
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sercom0: sercom@42000000 {
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compatible = "atmel,sam0-sercom";
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reg = <0x42000000 0x40>;
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status = "disabled";
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label = "SERCOM0";
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};
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sercom1: sercom@42000400 {
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compatible = "atmel,sam0-sercom";
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reg = <0x42000400 0x40>;
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status = "disabled";
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label = "SERCOM1";
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};
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sercom2: sercom@42000800 {
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compatible = "atmel,sam0-sercom";
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reg = <0x42000800 0x40>;
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status = "disabled";
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label = "SERCOM2";
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};
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sercom3: sercom@42000c00 {
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compatible = "atmel,sam0-sercom";
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reg = <0x42000C00 0x40>;
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status = "disabled";
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label = "SERCOM3";
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};
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sercom4: sercom@42001000 {
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compatible = "atmel,sam0-sercom";
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reg = <0x42001000 0x40>;
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status = "disabled";
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label = "SERCOM4";
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};
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sercom5: sercom@43000400 {
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compatible = "atmel,sam0-sercom";
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reg = <0x43000400 0x40>;
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status = "disabled";
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label = "SERCOM5";
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};
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tc4: tc@43000800 {
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compatible = "atmel,sam0-tc32";
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reg = <0x43000800 0x34>;
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label = "TIMER_4";
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};
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pinctrl: pinctrl@40002800 {
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compatible = "atmel,sam0-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x40002800 0x40002800 0x100>;
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porta: gpio@40002800 {
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compatible = "atmel,sam0-gpio";
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reg = <0x40002800 0x80>;
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label = "PORTA";
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gpio-controller;
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#gpio-cells = <2>;
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#atmel,pin-cells = <2>;
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};
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portb: gpio@40002880 {
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compatible = "atmel,sam0-gpio";
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reg = <0x40002880 0x80>;
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label = "PORTB";
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gpio-controller;
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#gpio-cells = <2>;
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#atmel,pin-cells = <2>;
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};
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};
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rtc: rtc@40002000 {
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compatible = "atmel,sam0-rtc";
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reg = <0x40002000 0x1c>;
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interrupts = <2 0>;
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clock-generator = <0>;
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status = "disabled";
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label = "RTC";
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};
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adc: adc@43000c00 {
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compatible = "atmel,sam0-adc";
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reg = <0x43000c00 0x30>;
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label = "ADC_0";
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/*
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* 16 MHz max, so clock it with the
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* 48 MHz DFLL / 2 / 2 = 12 MHz
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*/
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gclk = <3>;
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prescaler = <2>;
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#io-channel-cells = <1>;
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};
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dac: dac@42003000 {
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compatible = "atmel,sam0-dac";
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status = "disabled";
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reg = <0x42003000 0x1a>;
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label = "DAC_0";
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#io-channel-cells = <0>;
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};
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trng: random@42003800 {
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compatible = "atmel,sam-trng";
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reg = <0x42003800 0x24>;
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peripheral-id = <0>;
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interrupts = <27 0>;
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label = "ENTROPY_0";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <2>;
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};

‎dts/bindings/clock/atmel,saml2x-gclk.yaml‎

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# Copyright (c) 2021 Argentum Systems Ltd.
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# SPDX-License-Identifier: Apache-2.0
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description: Atmel SAML2x Generic Clock Controller (GCLK)
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compatible: "atmel,saml2x-gclk"
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include: [clock-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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"#clock-cells":
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const: 1
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clock-cells:
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- periph_ch

‎dts/bindings/clock/atmel,saml2x-mclk.yaml‎

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# Copyright (c) 2021 Argentum Systems Ltd.
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# SPDX-License-Identifier: Apache-2.0
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description: Atmel SAML2x Generic Clock Controller (MCLK)
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compatible: "atmel,saml2x-mclk"
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include: [clock-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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"#clock-cells":
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const: 2
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clock-cells:
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- offset
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- bit

‎soc/arm/atmel_sam0/Kconfig‎

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string
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default "atmel_sam0"
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source "soc/arm/atmel_sam0/common/Kconfig.saml2x"
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source "soc/arm/atmel_sam0/common/Kconfig.samd2x"
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source "soc/arm/atmel_sam0/common/Kconfig.samd5x"
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source "soc/arm/atmel_sam0/*/Kconfig.soc"

‎soc/arm/atmel_sam0/common/CMakeLists.txt‎

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@@ -10,6 +10,7 @@ zephyr_sources_ifdef(CONFIG_BOOTLOADER_BOSSA bossa.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD20 soc_samd2x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD21 soc_samd2x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMR21 soc_samd2x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAML21 soc_saml2x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD51 soc_samd5x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAME51 soc_samd5x.c)

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