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drivers: gpio: Add support for RZ/V2H
Add support for RZ/V2H Signed-off-by: Tien Nguyen <[email protected]> Signed-off-by: Quang Le <[email protected]>
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-26
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3 files changed

+200
-26
lines changed

‎drivers/gpio/gpio_renesas_rz.c

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -297,12 +297,12 @@ static int gpio_rz_int_disable(const struct device *dev, const struct device *gp
297297
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
298298
volatile uint32_t *tssr = &R_INTC->TSSR0;
299299
volatile uint32_t *titsr = &R_INTC->TITSR0;
300-
volatile uint32_t *tscr = &R_INTC->TSCR;
301300
struct gpio_rz_int_data *data = dev->data;
302301

303302
/* Get register offset base on interrupt number. */
304303
tssr = &tssr[int_num / 4];
305304
titsr = &titsr[int_num / 16];
305+
GPIO_RZ_TINT_SELECT_SOURCE_REG_CLEAR(int_num);
306306

307307
irq_disable(GPIO_RZ_TINT_IRQ_GET(int_num));
308308
/* Disable interrupt and clear interrupt source. */
@@ -312,7 +312,7 @@ static int gpio_rz_int_disable(const struct device *dev, const struct device *gp
312312

313313
/* Clear interrupt detection status. */
314314
if (data->irq_set_edge & BIT(int_num)) {
315-
*tscr &= ~BIT(int_num);
315+
GPIO_RZ_TINT_STATUS_REG_CLEAR(int_num);
316316
data->irq_set_edge &= ~BIT(int_num);
317317
}
318318

@@ -350,13 +350,18 @@ static int gpio_rz_int_enable(const struct device *gpio_int_dev, const struct de
350350
*titsr &= ~(3U << GPIO_RZ_TITSR_OFFSET(int_num));
351351
*titsr |= (irq_type << GPIO_RZ_TITSR_OFFSET(int_num));
352352
/* Select interrupt source base on port and pin number. */
353+
*tssr &= ~(0xFF << (int_num));
353354
*tssr |= (GPIO_RZ_TSSR_VAL(gpio_config->port_num, pin)) << GPIO_RZ_TSSR_OFFSET(int_num);
355+
/* Select TINT source(only for RZV2H) */
356+
GPIO_RZ_TINT_SELECT_SOURCE_REG_CLEAR(int_num);
357+
GPIO_RZ_TINT_SELECT_SOURCE_REG_SET(int_num);
354358

355359
if (irq_type == GPIO_RZ_INT_EDGE_RISING || irq_type == GPIO_RZ_INT_EDGE_FALLING) {
356360
gpio_int_data->irq_set_edge |= BIT(int_num);
357361
/* Clear interrupt status. */
358-
R_INTC->TSCR &= ~BIT(int_num);
362+
GPIO_RZ_TINT_STATUS_REG_CLEAR(int_num);
359363
}
364+
GPIO_RZ_TINT_CLEAR_PENDING(int_num);
360365
irq_enable(GPIO_RZ_TINT_IRQ_GET(int_num));
361366
gpio_int_data->gpio_mapping[int_num].gpio_dev = gpio_dev;
362367
gpio_int_data->gpio_mapping[int_num].pin = pin;
@@ -448,15 +453,16 @@ static void gpio_rz_isr(uint16_t irq, void *param)
448453
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
449454
const struct device *dev = param;
450455
struct gpio_rz_int_data *gpio_int_data = dev->data;
451-
volatile uint32_t *tscr = &R_INTC->TSCR;
452456

453-
if (!(*tscr & BIT(irq))) {
457+
#if GPIO_RZ_TINT_SPURIOUS_HANDLE
458+
if (!(*GPIO_RZ_TINT_STATUS_REG_GET & BIT(irq))) {
454459
LOG_DEV_DBG(dev, "tint:%u spurious irq, status 0", irq);
455460
return;
456461
}
462+
#endif /* GPIO_RZ_TINT_SPURIOUS_HANDLE */
457463

458464
if (gpio_int_data->irq_set_edge & BIT(irq)) {
459-
*tscr &= ~BIT(irq);
465+
GPIO_RZ_TINT_STATUS_REG_CLEAR(irq);
460466
}
461467

462468
uint8_t pin = gpio_int_data->gpio_mapping[irq].pin;

‎drivers/gpio/gpio_renesas_rz.h

Lines changed: 64 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -8,46 +8,88 @@
88
#define ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_
99

1010
#include "r_ioport.h"
11+
#include <zephyr/drivers/interrupt_controller/gic.h>
1112

1213
#define GPIO_RZ_INT_UNSUPPORTED 0xF
1314

1415
#if defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL) || \
15-
defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L)
16+
defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L) || \
17+
defined(CONFIG_SOC_SERIES_RZV2H)
1618
#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
1719

1820
#if defined(CONFIG_SOC_SERIES_RZG3S)
19-
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P_20)
20-
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM_20)
21-
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC_20)
22-
#define GPIO_RZ_MAX_PORT_NUM 19
23-
#define GPIO_RZ_TINT_IRQ_OFFSET 429
24-
#define R_INTC R_INTC_IM33
21+
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P_20)
22+
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM_20)
23+
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC_20)
24+
#define GPIO_RZ_MAX_PORT_NUM 19
25+
#define GPIO_RZ_TINT_IRQ_OFFSET 429
26+
#define R_INTC R_INTC_IM33
27+
#define GPIO_RZ_TINT_STATUS_REG_CLEAR(tint_num) (R_INTC_IM33->TSCR &= ~BIT(tint_num))
2528
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43,
2629
47, 52, 56, 58, 63, 66, 70, 72, 76};
2730

2831
#elif defined(CONFIG_SOC_SERIES_RZA3UL)
29-
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P10)
30-
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM10)
31-
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC10)
32-
#define GPIO_RZ_MAX_PORT_NUM 19
33-
#define GPIO_RZ_TINT_IRQ_OFFSET 476
34-
#define R_INTC R_INTC_IA55
32+
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P10)
33+
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM10)
34+
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC10)
35+
#define GPIO_RZ_MAX_PORT_NUM 19
36+
#define GPIO_RZ_TINT_IRQ_OFFSET 476
37+
#define R_INTC R_INTC_IA55
38+
#define GPIO_RZ_TINT_STATUS_REG_CLEAR(tint_num) (R_INTC_IA55->TSCR &= ~BIT(tint_num))
3539
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43,
3640
47, 52, 56, 58, 63, 66, 70, 72, 76};
3741

42+
#elif defined(CONFIG_SOC_SERIES_RZV2H)
43+
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P20)
44+
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM20)
45+
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC20)
46+
#define GPIO_RZ_TINT_STATUS_REG_GET (&R_INTC->TSCTR)
47+
48+
#ifdef CONFIG_CPU_CORTEX_M
49+
#define GPIO_RZ_TINT_IRQ_OFFSET 353
50+
#define GPIO_RZ_TINT_SPURIOUS_HANDLE 0
51+
#define GPIO_RZ_TINT_SELECT_SOURCE_REG_GET (&R_INTC->INTM33SEL0)
52+
#else /* Cortex-R */
53+
#define GPIO_RZ_TINT_IRQ_OFFSET (GIC_SPI_INT_BASE + 353)
54+
#define GPIO_RZ_TINT_SELECT_SOURCE_REG_GET (&R_INTC->INTR8SEL0)
55+
#endif
56+
57+
#define GPIO_RZ_MAX_PORT_NUM 12
58+
#define GPIO_RZ_TINT_STATUS_REG_CLEAR(tint_num) (R_INTC->TSCLR |= BIT(tint_num))
59+
#define GPIO_RZ_TINT_SELECT_SOURCE_REG_CLEAR(tint_num) \
60+
GPIO_RZ_TINT_SELECT_SOURCE_REG_GET[int_num / 3] &= ~(0x3FF << ((int_num % 3) * 10));
61+
#define GPIO_RZ_TINT_SELECT_SOURCE_REG_SET(tint_num) \
62+
GPIO_RZ_TINT_SELECT_SOURCE_REG_GET[int_num / 3] |= (int_num << ((int_num % 3) * 10));
63+
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 8, 14, 16, 24, 32,
64+
40, 48, 56, 64, 72, 80};
65+
3866
#elif defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L)
39-
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P10)
40-
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM10)
41-
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC10)
42-
#define GPIO_RZ_MAX_PORT_NUM 49
43-
#define GPIO_RZ_TINT_IRQ_OFFSET 444
44-
#define R_INTC R_INTC_IM33
67+
#define GPIO_RZ_P_REG_BASE_GET (&R_GPIO->P10)
68+
#define GPIO_RZ_PM_REG_BASE_GET (&R_GPIO->PM10)
69+
#define GPIO_RZ_PFC_REG_BASE_GET (&R_GPIO->PFC10)
70+
#define GPIO_RZ_MAX_PORT_NUM 49
71+
#define GPIO_RZ_TINT_IRQ_OFFSET 444
72+
#define R_INTC R_INTC_IM33
73+
#define GPIO_RZ_TINT_STATUS_REG_CLEAR(tint_num) (R_INTC_IM33->TSCR &= ~BIT(tint_num))
4574
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {
4675
0, 2, 4, 6, 8, 10, 13, 15, 18, 21, 24, 25, 27, 29, 32, 34, 36,
4776
38, 41, 43, 45, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72,
4877
74, 76, 78, 80, 83, 85, 88, 91, 93, 98, 102, 106, 110, 114, 118};
4978
#endif
5079

80+
#ifndef GPIO_RZ_TINT_SELECT_SOURCE_REG_CLEAR
81+
#define GPIO_RZ_TINT_SELECT_SOURCE_REG_CLEAR(tint_num)
82+
#define GPIO_RZ_TINT_SELECT_SOURCE_REG_SET(tint_num)
83+
#endif
84+
85+
#ifndef GPIO_RZ_TINT_STATUS_REG_GET
86+
#define GPIO_RZ_TINT_STATUS_REG_GET (&R_INTC->TSCR)
87+
#endif
88+
89+
#ifndef GPIO_RZ_TINT_SPURIOUS_HANDLE
90+
#define GPIO_RZ_TINT_SPURIOUS_HANDLE 1
91+
#endif
92+
5193
#define GPIO_RZ_P_REG_GET(port, pin) (&GPIO_RZ_P_REG_BASE_GET[port])
5294
#define GPIO_RZ_PM_REG_GET(port, pin) (&GPIO_RZ_PM_REG_BASE_GET[port])
5395
#define GPIO_RZ_PFC_REG_GET(port, pin) (&GPIO_RZ_PFC_REG_BASE_GET[port])
@@ -60,7 +102,8 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {
60102

61103
#define GPIO_RZ_MAX_INT_NUM 32
62104

63-
#define GPIO_RZ_TINT_IRQ_GET(tint_num) (tint_num + GPIO_RZ_TINT_IRQ_OFFSET)
105+
#define GPIO_RZ_TINT_IRQ_GET(tint_num) (tint_num + GPIO_RZ_TINT_IRQ_OFFSET)
106+
#define GPIO_RZ_TINT_CLEAR_PENDING(tint_num) R_BSP_IrqClearPending(GPIO_RZ_TINT_IRQ_GET(tint_num))
64107

65108
#define GPIO_RZ_INT_EDGE_RISING 0x0
66109
#define GPIO_RZ_INT_EDGE_FALLING 0x1
@@ -116,6 +159,7 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {
116159
#define GPIO_RZ_INT_LEVEL_HIGH GPIO_RZ_INT_UNSUPPORTED
117160
#define GPIO_RZ_INT_ENABLE (1U << 3)
118161
#define GPIO_RZ_INT_DISABLE (~(1U << 3))
162+
#define GPIO_RZ_TINT_CLEAR_PENDING(int_num)
119163

120164
#define GPIO_RZ_FLAG_GET_CONFIG(flag) (((flag >> RZTN_GPIO_DRCTL_SHIFT) & 0x33) << 8U)
121165
#define GPIO_RZ_FLAG_SET_PFC(value) (value << 4)

‎dts/arm/renesas/rz/rzv/r9a09g057_cm33.dtsi

Lines changed: 124 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,130 @@
3636
compatible = "renesas,rzv-pinctrl";
3737
reg = <0x40410000 DT_SIZE_K(64)>;
3838
reg-names = "pinctrl";
39+
40+
gpio: gpio-common {
41+
compatible = "renesas,rz-gpio-int";
42+
interrupts =
43+
<353 10>, <354 10>, <355 10>, <356 10>,
44+
<357 10>, <358 10>, <359 10>, <360 10>,
45+
<361 10>, <362 10>, <363 10>, <364 10>,
46+
<365 10>, <366 10>, <367 10>, <368 10>,
47+
<369 10>, <370 10>, <371 10>, <372 10>,
48+
<373 10>, <374 10>, <375 10>, <376 10>,
49+
<377 10>, <378 10>, <379 10>, <380 10>,
50+
<381 10>, <382 10>, <383 10>, <384 10>;
51+
#address-cells = <1>;
52+
#size-cells = <0>;
53+
status = "disabled";
54+
55+
gpio0: gpio@0 {
56+
compatible = "renesas,rz-gpio";
57+
gpio-controller;
58+
#gpio-cells = <2>;
59+
ngpios = <8>;
60+
reg = <0x0>;
61+
status = "disabled";
62+
};
63+
64+
gpio1: gpio@100 {
65+
compatible = "renesas,rz-gpio";
66+
gpio-controller;
67+
#gpio-cells = <2>;
68+
ngpios = <6>;
69+
reg = <0x100>;
70+
status = "disabled";
71+
};
72+
73+
gpio2: gpio@200 {
74+
compatible = "renesas,rz-gpio";
75+
gpio-controller;
76+
#gpio-cells = <2>;
77+
ngpios = <2>;
78+
reg = <0x200>;
79+
status = "disabled";
80+
};
81+
82+
gpio3: gpio@300 {
83+
compatible = "renesas,rz-gpio";
84+
gpio-controller;
85+
#gpio-cells = <2>;
86+
ngpios = <8>;
87+
reg = <0x300>;
88+
status = "disabled";
89+
};
90+
91+
gpio4: gpio@400 {
92+
compatible = "renesas,rz-gpio";
93+
gpio-controller;
94+
#gpio-cells = <2>;
95+
ngpios = <8>;
96+
reg = <0x400>;
97+
status = "disabled";
98+
};
99+
100+
gpio5: gpio@500 {
101+
compatible = "renesas,rz-gpio";
102+
gpio-controller;
103+
#gpio-cells = <2>;
104+
ngpios = <8>;
105+
reg = <0x500>;
106+
status = "disabled";
107+
};
108+
109+
gpio6: gpio@600 {
110+
compatible = "renesas,rz-gpio";
111+
gpio-controller;
112+
#gpio-cells = <2>;
113+
ngpios = <8>;
114+
reg = <0x600>;
115+
status = "disabled";
116+
};
117+
118+
gpio7: gpio@700 {
119+
compatible = "renesas,rz-gpio";
120+
gpio-controller;
121+
#gpio-cells = <2>;
122+
ngpios = <8>;
123+
reg = <0x700>;
124+
status = "disabled";
125+
};
126+
127+
gpio8: gpio@800 {
128+
compatible = "renesas,rz-gpio";
129+
gpio-controller;
130+
#gpio-cells = <2>;
131+
ngpios = <8>;
132+
reg = <0x800>;
133+
status = "disabled";
134+
};
135+
136+
gpio9: gpio@900 {
137+
compatible = "renesas,rz-gpio";
138+
gpio-controller;
139+
#gpio-cells = <2>;
140+
ngpios = <8>;
141+
reg = <0x900>;
142+
status = "disabled";
143+
};
144+
145+
gpio10: gpio@a00 {
146+
compatible = "renesas,rz-gpio";
147+
gpio-controller;
148+
#gpio-cells = <2>;
149+
ngpios = <8>;
150+
reg = <0xa00>;
151+
status = "disabled";
152+
};
153+
154+
gpio11: gpio@b00 {
155+
compatible = "renesas,rz-gpio";
156+
gpio-controller;
157+
#gpio-cells = <2>;
158+
ngpios = <6>;
159+
reg = <0xb00>;
160+
status = "disabled";
161+
};
162+
};
39163
};
40164

41165
sci0: sci0@42800c00 {

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