drivers: pinctrl: Add ZynqMP / Mercury XU pinctrl support

Add a pinctrl driver for the ZynqMP SoC and the
Mercury XU board powered by it.

Signed-off-by: Jan Bylicki <[email protected]>

Author: jbylicki

drivers/pinctrl/CMakeLists.txt

@@ -26,6 +26,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_ESP32 pinctrl_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_INFINEON_CAT1 pinctrl_ifx_cat1.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_XLNX_ZYNQ pinctrl_xlnx_zynq.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_XLNX_ZYNQMP pinctrl_xlnx_zynqmp.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND pinctrl_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_XMC4XXX pinctrl_xmc4xxx.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_S32 pinctrl_nxp_s32.c)

drivers/pinctrl/Kconfig

@@ -66,5 +66,6 @@ source "drivers/pinctrl/Kconfig.numaker"
 source "drivers/pinctrl/Kconfig.eos_s3"
 source "drivers/pinctrl/Kconfig.ra"
 source "drivers/pinctrl/Kconfig.rzt2m"
+source "drivers/pinctrl/Kconfig.zynqmp"
 
 endif # PINCTRL

drivers/pinctrl/Kconfig.zynqmp

@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_XLNX_ZYNQMP
+	bool "Xilinx ZynqMP pin controller driver"
+	default y
+	depends on DT_HAS_XLNX_PINCTRL_ZYNQMP_ENABLED
+	help
+	  Enable the Xilinx ZynqMP processor system MIO pin controller driver.

drivers/pinctrl/pinctrl_xlnx_zynqmp.c

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2024 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <zephyr/logging/log.h>
+#include "pinctrl_soc.h"
+
+LOG_MODULE_REGISTER(pinctrl_xlnx_zynqmp, CONFIG_PINCTRL_LOG_LEVEL);
+
+#define DT_DRV_COMPAT xlnx_pinctrl_zynqmp
+
+static mm_reg_t base = DT_INST_REG_ADDR(0);
+static uint8_t mio_pin_offset = 0x04;
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
+{
+	for (uint8_t i = 0U; i < pin_cnt; i++) {
+		uint32_t sel = 0;
+
+		switch (pins[i].func) {
+			case UART_FUNCTION: {
+				sel = UARTX_SEL;
+				break;
+			}
+
+			default: {
+				LOG_ERR("Unsupported function enum was selected");
+				break;
+			}
+		}
+		sys_write32(sel, base + mio_pin_offset * pins[i].pin);
+	}
+
+	return 0;
+}

dts/arm/xilinx/zynqmp.dtsi

@@ -11,6 +11,10 @@
 
 / {
 	soc {
+		pinctrl: pinctrl@ff180000 {
+			reg = <0xff180000 0xc80>;
+			compatible = "xlnx,pinctrl-zynqmp";
+		};
 		flash0: flash@c0000000 {
 			compatible = "soc-nv-flash";
 			reg = <0xc0000000 DT_SIZE_M(32)>;
@@ -271,4 +275,5 @@
 			};
 		};
 	};
+
 };

dts/bindings/pinctrl/xlnx,pinctrl-zynqmp.yaml

@@ -0,0 +1,27 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Xilinx ZynqMP SoC pinctrl node. It allows configuration of pin assignments
+  for the supported peripherals.
+
+  See Zynq UltraScale+ Devices Register Reference (UG1087) for details regarding
+  valid pin assignments
+compatible: "xlnx,pinctrl-zynqmp"
+
+include: base.yaml
+
+child-binding:
+  description: |
+    Definitions for a pinctrl state.
+  child-binding:
+
+    include:
+      - name: pincfg-node.yaml
+
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+            Pin assignments for the selected group

include/zephyr/dt-bindings/pinctrl/pinctrl-zynqmp.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ZYNQMP_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ZYNQMP_PINCTRL_H_
+
+#define UART_FUNCTION 0x1
+
+#define UART0_RX_38 (38U | (UART_FUNCTION << 8))
+#define UART0_TX_39 (39U | (UART_FUNCTION << 8))
+
+
+#endif

soc/arm/xilinx_zynqmp/pinctrl_soc.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2024 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_ARM_XLNX_ZYNQMP_SOC_PINCTRL_H_
+#define ZEPHYR_SOC_ARM_XLNX_ZYNQMP_SOC_PINCTRL_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/types.h>
+
+#define MIO_L0_SEL     BIT(1)
+#define MIO_L1_SEL     BIT(2)
+#define MIO_L2_SEL     GENMASK(4, 3)
+#define MIO_L3_SEL     GENMASK(7, 5)
+
+/* All other selectors should be zeroed and FIELD_PREP does that */
+#define UARTX_SEL FIELD_PREP(MIO_L3_SEL, 6)
+
+/*
+ * Each peripheral PINCTRL mask is defined as such:
+ * [7 ... 0]  MIO register number
+ * [15 ... 8] Function, mapped as:
+ *     1 - UART
+ *
+ * The function numbers serve as an enumerator in the pinctrl driver
+ * and the defines controling those are listed in `pinctrl-zynqmp.h`.
+ * Currently, one function for UART is specified and subsequent ones
+ * can be added when the need arises.
+ */
+
+typedef struct pinctrl_soc_pin_t {
+	uint32_t pin;
+	uint32_t func;
+} pinctrl_soc_pin_t;
+
+
+#define ZYNQMP_GET_PIN(pinctrl)  (pinctrl & 0xff)
+#define ZYNQMP_GET_FUNC(pinctrl) ((pinctrl >> 8) & 0xff)
+
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
+		{ \
+				.pin = ZYNQMP_GET_PIN(DT_PROP_BY_IDX(node_id, prop, idx)), \
+				.func = ZYNQMP_GET_FUNC(DT_PROP_BY_IDX(node_id, prop, idx)), \
+		},
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) { \
+				DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
+				DT_FOREACH_PROP_ELEM, pinmux, \
+				Z_PINCTRL_STATE_PIN_INIT)}
+
+#endif