intel_adsp: tlb: Configure HPSRAM retention mode after power transitions

Explicitly configure retention mode when powering up HPSRAM banks to
ensure consistent behavior across hardware platforms.

After D3 power state transitions, the retention mode configuration can
become undefined due to hardware reset. This causes test failures in NVL
FPGA testing environment where the hardware strictly enforces retention
mode settings.

The fix ensures retention mode is properly set in two locations:
- sys_mm_drv_hpsram_pwr(): Configure retention mode for all bank
  power-up operations
- adsp_mm_restore_context(): Explicitly set retention mode during
  D3->D0 restore sequence after each bank is powered up

Signed-off-by: Tomasz Leman <[email protected]>

Author: tmleman

drivers/mm/mm_drv_intel_adsp_mtl_tlb.c

@@ -149,6 +149,10 @@ static int sys_mm_drv_hpsram_pwr(uint32_t bank_idx, bool enable, bool non_blocki
 
 	HPSRAM_REGS(bank_idx)->HSxPGCTL = !enable;
 
+	if (enable) {
+		HPSRAM_REGS(bank_idx)->HSxRMCTL = IS_ENABLED(CONFIG_SRAM_RETENTION_MODE);
+	}
+
 	if (!non_blocking) {
 		while (HPSRAM_REGS(bank_idx)->HSxPGISTS == enable) {
 			k_busy_wait(1);
@@ -911,6 +915,7 @@ __imr void adsp_mm_restore_context(void *storage_buffer)
 		/* turn on memory bank power, wait till the power is on */
 		__ASSERT_NO_MSG(bank_idx <= ace_hpsram_get_bank_count());
 		HPSRAM_REGS(bank_idx)->HSxPGCTL = 0;
+		HPSRAM_REGS(bank_idx)->HSxRMCTL = IS_ENABLED(CONFIG_SRAM_RETENTION_MODE);
 		while (HPSRAM_REGS(bank_idx)->HSxPGISTS == 1) {
 			/* k_busy_wait cannot be used here - not available */
 		}