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laurenmurphyx64nashif
laurenmurphyx64
authored and
nashif
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boards, dts: fix filenames and dts refs for adsp clock
Changes filenames and DTS references from CAVS clock to ADSP clock. Signed-off-by: Lauren Murphy <[email protected]>
1 parent 1983a4c commit 8544547

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12 files changed

+44
-44
lines changed

12 files changed

+44
-44
lines changed

‎drivers/clock_control/CMakeLists.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
zephyr_library()
44

55
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c)
6-
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ADSP clock_control_cavs.c)
6+
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ADSP clock_control_adsp.c)
77
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32 clock_control_esp32.c)
88
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_GD32 clock_control_gd32.c)
99
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX clock_control_litex.c)

‎drivers/clock_control/clock_control_cavs.c‎ renamed to ‎drivers/clock_control/clock_control_adsp.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66
#include <zephyr/device.h>
7-
#include <zephyr/drivers/clock_control/clock_control_cavs.h>
7+
#include <zephyr/drivers/clock_control/clock_control_adsp.h>
88
#include <zephyr/drivers/clock_control.h>
99

1010
static int cavs_clock_ctrl_set_rate(const struct device *clk,

‎dts/bindings/clock/intel,adsp-shim-clkctl.yaml‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,42 +1,42 @@
11
# Copyright (c) 2022 Intel Corporation. All rights reserved.
22
# SPDX-License-Identifier: Apache-2.0
33

4-
description: Intel cAVS clock controlling related constants.
4+
description: Intel ADSP clock controlling related constants.
55

66
compatible: "intel,adsp-shim-clkctl"
77

88
properties:
9-
cavs-clkctl-clk-wovcro:
9+
adsp-clkctl-clk-wovcro:
1010
type: int
1111
required: false
1212
description: Index of WOVCRO clock encoding in the encoding array (if wovcro-supported is true).
1313

14-
cavs-clkctl-clk-lpro:
14+
adsp-clkctl-clk-lpro:
1515
type: int
1616
required: false
1717
description: Index of LPRO clock encoding in the encoding array.
1818

19-
cavs-clkctl-clk-hpro:
19+
adsp-clkctl-clk-hpro:
2020
type: int
2121
required: false
2222
description: Index of HPRO clock encoding in the encoding array.
2323

24-
cavs-clkctl-freq-enc:
24+
adsp-clkctl-freq-enc:
2525
type: array
2626
required: true
2727
description: Array that encodes what is needed to enable each clock.
2828

29-
cavs-clkctl-freq-mask:
29+
adsp-clkctl-freq-mask:
3030
type: array
3131
required: false
3232
description: Array that encodes needed masks to enable each clock.
3333

34-
cavs-clkctl-freq-default:
34+
adsp-clkctl-freq-default:
3535
type: int
3636
required: true
3737
description: Index for the default clock.
3838

39-
cavs-clkctl-freq-lowest:
39+
adsp-clkctl-freq-lowest:
4040
type: int
4141
required: true
4242
description: Index for the lowest frequency clock.

‎dts/xtensa/intel/intel_adsp_cavs15.dtsi‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -55,11 +55,11 @@
5555

5656
clkctl: clkctl {
5757
compatible = "intel,adsp-shim-clkctl";
58-
cavs-clkctl-clk-lpro = <0>;
59-
cavs-clkctl-clk-hpro = <2>;
60-
cavs-clkctl-freq-enc = <0x3 0x1 0x0>;
61-
cavs-clkctl-freq-default = <1>;
62-
cavs-clkctl-freq-lowest = <0>;
58+
adsp-clkctl-clk-lpro = <0>;
59+
adsp-clkctl-clk-hpro = <2>;
60+
adsp-clkctl-freq-enc = <0x3 0x1 0x0>;
61+
adsp-clkctl-freq-default = <1>;
62+
adsp-clkctl-freq-lowest = <0>;
6363
};
6464

6565
soc {

‎dts/xtensa/intel/intel_adsp_cavs18.dtsi‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -51,12 +51,12 @@
5151

5252
clkctl: clkctl {
5353
compatible = "intel,adsp-shim-clkctl";
54-
cavs-clkctl-clk-lpro = <0>;
55-
cavs-clkctl-clk-hpro = <1>;
56-
cavs-clkctl-freq-enc = <0x20000002 0x80000006>;
57-
cavs-clkctl-freq-mask = <0x20000000 0x80000000>;
58-
cavs-clkctl-freq-default = <1>;
59-
cavs-clkctl-freq-lowest = <0>;
54+
adsp-clkctl-clk-lpro = <0>;
55+
adsp-clkctl-clk-hpro = <1>;
56+
adsp-clkctl-freq-enc = <0x20000002 0x80000006>;
57+
adsp-clkctl-freq-mask = <0x20000000 0x80000000>;
58+
adsp-clkctl-freq-default = <1>;
59+
adsp-clkctl-freq-lowest = <0>;
6060
};
6161

6262
soc {

‎dts/xtensa/intel/intel_adsp_cavs20.dtsi‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -51,12 +51,12 @@
5151

5252
clkctl: clkctl {
5353
compatible = "intel,adsp-shim-clkctl";
54-
cavs-clkctl-clk-lpro = <0>;
55-
cavs-clkctl-clk-hpro = <1>;
56-
cavs-clkctl-freq-enc = <0x20000002 0x80000006>;
57-
cavs-clkctl-freq-mask = <0x20000000 0x80000000>;
58-
cavs-clkctl-freq-default = <1>;
59-
cavs-clkctl-freq-lowest = <0>;
54+
adsp-clkctl-clk-lpro = <0>;
55+
adsp-clkctl-clk-hpro = <1>;
56+
adsp-clkctl-freq-enc = <0x20000002 0x80000006>;
57+
adsp-clkctl-freq-mask = <0x20000000 0x80000000>;
58+
adsp-clkctl-freq-default = <1>;
59+
adsp-clkctl-freq-lowest = <0>;
6060
};
6161

6262
soc {

‎dts/xtensa/intel/intel_adsp_cavs25.dtsi‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -69,13 +69,13 @@
6969

7070
clkctl: clkctl {
7171
compatible = "intel,adsp-shim-clkctl";
72-
cavs-clkctl-clk-wovcro = <0>;
73-
cavs-clkctl-clk-lpro = <1>;
74-
cavs-clkctl-clk-hpro = <2>;
75-
cavs-clkctl-freq-enc = <0x1a 0x20000002 0x80000002>;
76-
cavs-clkctl-freq-mask = <0x10 0x20000000 0x80000000>;
77-
cavs-clkctl-freq-default = <2>;
78-
cavs-clkctl-freq-lowest = <0>;
72+
adsp-clkctl-clk-wovcro = <0>;
73+
adsp-clkctl-clk-lpro = <1>;
74+
adsp-clkctl-clk-hpro = <2>;
75+
adsp-clkctl-freq-enc = <0x1a 0x20000002 0x80000002>;
76+
adsp-clkctl-freq-mask = <0x10 0x20000000 0x80000000>;
77+
adsp-clkctl-freq-default = <2>;
78+
adsp-clkctl-freq-lowest = <0>;
7979
wovcro-supported;
8080
};
8181

‎include/zephyr/drivers/clock_control/clock_control_cavs.h‎ renamed to ‎include/zephyr/drivers/clock_control/clock_control_adsp.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,6 @@
66
#ifndef CLOCK_CONTROL_ADSP_H_
77
#define CLOCK_CONTROL_ADSP_H_
88

9-
#include <cavs-clk.h>
9+
#include <adsp-clk.h>
1010

1111
#endif /* CLOCK_CONTROL_ADSP_H_ */

‎soc/xtensa/intel_adsp/cavs/power.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
#include <zephyr/init.h>
1212

1313
#include <adsp_shim.h>
14-
#include <cavs-clk.h>
14+
#include <adsp-clk.h>
1515
#include <cavs-idc.h>
1616
#include "soc.h"
1717

‎soc/xtensa/intel_adsp/common/clk.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
*/
66
#include <zephyr/device.h>
77

8-
#include <cavs-clk.h>
8+
#include <adsp-clk.h>
99
#include <adsp_shim.h>
1010

1111
static struct cavs_clock_info platform_clocks[CONFIG_MP_NUM_CPUS];

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