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include/dt-bindings/clock: stm32: Add clock sources bindings
Add clock sources bindings on F0/F3/G0/G4/L0/L1/L4/WB/WL series. Due to inconsistencies, some common bindings are now split: F1 -> F0/F1/F3 L4 -> L4/G4/WB Update .dtsi files when required In a first step, allowed sources are limited to already supported clocks: LSI/LSE/HSI/HSE/MSI/PCLK/PLLCLK/SYSCLK Support for other clocks such as HSI48, SAIXCLK, ... is left for a next step. Signed-off-by: Erwan Gouriou <[email protected]>
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15 files changed

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‎dts/arm/st/f0/stm32f0.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
*/
77

88
#include <arm/armv6-m.dtsi>
9-
#include <zephyr/dt-bindings/clock/stm32f1_clock.h>
9+
#include <zephyr/dt-bindings/clock/stm32f0_clock.h>
1010
#include <zephyr/dt-bindings/i2c/i2c.h>
1111
#include <zephyr/dt-bindings/gpio/gpio.h>
1212
#include <zephyr/dt-bindings/pwm/pwm.h>

‎dts/arm/st/f3/stm32f3.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
*/
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88
#include <arm/armv7-m.dtsi>
9-
#include <zephyr/dt-bindings/clock/stm32f1_clock.h>
9+
#include <zephyr/dt-bindings/clock/stm32f3_clock.h>
1010
#include <zephyr/dt-bindings/i2c/i2c.h>
1111
#include <zephyr/dt-bindings/gpio/gpio.h>
1212
#include <zephyr/dt-bindings/pwm/pwm.h>

‎dts/arm/st/g4/stm32g4.dtsi‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
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88

99
#include <arm/armv7-m.dtsi>
10-
#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
10+
#include <zephyr/dt-bindings/clock/stm32g4_clock.h>
1111
#include <zephyr/dt-bindings/i2c/i2c.h>
1212
#include <zephyr/dt-bindings/gpio/gpio.h>
1313
#include <zephyr/dt-bindings/pwm/pwm.h>
@@ -51,9 +51,8 @@
5151

5252
clk_lse: clk-lse {
5353
#clock-cells = <0>;
54-
compatible = "st,stm32-lse-clock";
54+
compatible = "fixed-clock";
5555
clock-frequency = <32768>;
56-
driving-capability = <0>;
5756
status = "disabled";
5857
};
5958

@@ -354,7 +353,7 @@
354353
};
355354

356355
can {
357-
compatible = "bosch,m_can-base";
356+
compatible = "bosch,m-can-base";
358357
#address-cells = <1>;
359358
#size-cells = <1>;
360359
std-filter-elements = <28>;

‎dts/arm/st/wb/stm32wb.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
*/
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#include <arm/armv7-m.dtsi>
9-
#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
9+
#include <zephyr/dt-bindings/clock/stm32wb_clock.h>
1010
#include <zephyr/dt-bindings/gpio/gpio.h>
1111
#include <zephyr/dt-bindings/i2c/i2c.h>
1212
#include <zephyr/dt-bindings/pwm/pwm.h>

‎include/zephyr/drivers/clock_control/stm32_clock_control.h‎

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -11,25 +11,29 @@
1111

1212
#include <zephyr/drivers/clock_control.h>
1313

14-
#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
15-
defined(CONFIG_SOC_SERIES_STM32F1X) || \
16-
defined(CONFIG_SOC_SERIES_STM32F3X)
14+
#if defined(CONFIG_SOC_SERIES_STM32F0X)
15+
#include <zephyr/dt-bindings/clock/stm32f0_clock.h>
16+
#elif defined(CONFIG_SOC_SERIES_STM32F1X)
1717
#include <zephyr/dt-bindings/clock/stm32f1_clock.h>
18+
#elif defined(CONFIG_SOC_SERIES_STM32F3X)
19+
#include <zephyr/dt-bindings/clock/stm32f3_clock.h>
1820
#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
1921
defined(CONFIG_SOC_SERIES_STM32F4X) || \
2022
defined(CONFIG_SOC_SERIES_STM32F7X)
2123
#include <zephyr/dt-bindings/clock/stm32f4_clock.h>
2224
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
2325
#include <zephyr/dt-bindings/clock/stm32g0_clock.h>
26+
#elif defined(CONFIG_SOC_SERIES_STM32G4X)
27+
#include <zephyr/dt-bindings/clock/stm32g4_clock.h>
2428
#elif defined(CONFIG_SOC_SERIES_STM32L0X)
2529
#include <zephyr/dt-bindings/clock/stm32l0_clock.h>
2630
#elif defined(CONFIG_SOC_SERIES_STM32L1X)
2731
#include <zephyr/dt-bindings/clock/stm32l1_clock.h>
28-
#elif defined(CONFIG_SOC_SERIES_STM32G4X) || \
29-
defined(CONFIG_SOC_SERIES_STM32L4X) || \
30-
defined(CONFIG_SOC_SERIES_STM32L5X) || \
31-
defined(CONFIG_SOC_SERIES_STM32WBX)
32+
#elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
33+
defined(CONFIG_SOC_SERIES_STM32L5X)
3234
#include <zephyr/dt-bindings/clock/stm32l4_clock.h>
35+
#elif defined(CONFIG_SOC_SERIES_STM32WBX)
36+
#include <zephyr/dt-bindings/clock/stm32wb_clock.h>
3337
#elif defined(CONFIG_SOC_SERIES_STM32WLX)
3438
#include <zephyr/dt-bindings/clock/stm32wl_clock.h>
3539
#elif defined(CONFIG_SOC_SERIES_STM32H7X)

‎include/zephyr/dt-bindings/clock/stm32f0_clock.h‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,75 @@
1+
/*
2+
* Copyright (c) 2022 Linaro Limited
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
7+
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
8+
9+
/** Bus gatting clocks */
10+
#define STM32_CLOCK_BUS_AHB1 0x014
11+
#define STM32_CLOCK_BUS_APB2 0x018
12+
#define STM32_CLOCK_BUS_APB1 0x01c
13+
14+
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
15+
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
16+
17+
/** Peripheral clock sources */
18+
19+
/** Fixed clocks */
20+
#define STM32_SRC_HSI 0x001
21+
#define STM32_SRC_LSE 0x002
22+
/* #define STM32_SRC_HSI48 0x003 */
23+
/** System clock */
24+
#define STM32_SRC_SYSCLK 0x004
25+
/** Bus clock */
26+
#define STM32_SRC_PCLK 0x005
27+
/** PLL clock */
28+
#define STM32_SRC_PLLCLK 0x006
29+
30+
#define STM32_SRC_CLOCK_MIN STM32_SRC_HSI
31+
#define STM32_SRC_CLOCK_MAX STM32_SRC_PLLCLK
32+
33+
/**
34+
* @brief STM32 clock configuration bit field.
35+
*
36+
* - reg (1/2/3) [ 0 : 7 ]
37+
* - shift (0..31) [ 8 : 12 ]
38+
* - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
39+
* - val (0..7) [ 16 : 18 ]
40+
*
41+
* @param reg RCC_CFGRx register offset
42+
* @param shift Position within RCC_CFGRx.
43+
* @param mask Mask for the RCC_CFGRx field.
44+
* @param val Clock value (0, 1, ... 7).
45+
*/
46+
47+
#define STM32_CLOCK_REG_MASK 0xFFU
48+
#define STM32_CLOCK_REG_SHIFT 0U
49+
#define STM32_CLOCK_SHIFT_MASK 0x1FU
50+
#define STM32_CLOCK_SHIFT_SHIFT 8U
51+
#define STM32_CLOCK_MASK_MASK 0x7U
52+
#define STM32_CLOCK_MASK_SHIFT 13U
53+
#define STM32_CLOCK_VAL_MASK 0x7U
54+
#define STM32_CLOCK_VAL_SHIFT 16U
55+
56+
#define STM32_CLOCK(val, mask, shift, reg) \
57+
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
58+
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
59+
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
60+
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
61+
62+
/** @brief RCC_CFGRx register offset */
63+
#define CFGR3_REG 0x30
64+
65+
/** @brief Device clk sources selection helpers */
66+
/** CFGR3 devices */
67+
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG)
68+
#define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG)
69+
#define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CFGR3_REG)
70+
#define USB_SEL(val) STM32_CLOCK(val, 1, 7, CFGR3_REG)
71+
#define ADC_SEL(val) STM32_CLOCK(val, 1, 8, CFGR3_REG)
72+
#define USART2_SEL(val) STM32_CLOCK(val, 3, 16, CFGR3_REG)
73+
#define USART3_SEL(val) STM32_CLOCK(val, 3, 18, CFGR3_REG)
74+
75+
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ */

‎include/zephyr/dt-bindings/clock/stm32f3_clock.h‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,85 @@
1+
/*
2+
* Copyright (c) 2022 Linaro Limited
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
7+
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
8+
9+
/** Bus gatting clocks */
10+
#define STM32_CLOCK_BUS_AHB1 0x014
11+
#define STM32_CLOCK_BUS_APB2 0x018
12+
#define STM32_CLOCK_BUS_APB1 0x01c
13+
14+
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1
15+
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
16+
17+
/** Peripheral clock sources */
18+
/* RM0316, §9.4.13 Clock configuration register (RCC_CFGR3) */
19+
20+
/** Fixed clocks */
21+
#define STM32_SRC_HSI 0x001
22+
#define STM32_SRC_LSE 0x002
23+
/* #define STM32_SRC_HSI48 0x003 */
24+
/** System clock */
25+
#define STM32_SRC_SYSCLK 0x004
26+
/** Bus clock */
27+
#define STM32_SRC_PCLK 0x005
28+
/** PLL clock */
29+
#define STM32_SRC_PLLCLK 0x006
30+
31+
#define STM32_SRC_CLOCK_MIN STM32_SRC_HSI
32+
#define STM32_SRC_CLOCK_MAX STM32_SRC_PLLCLK
33+
34+
/**
35+
* @brief STM32 clock configuration bit field.
36+
*
37+
* - reg (1/2/3) [ 0 : 7 ]
38+
* - shift (0..31) [ 8 : 12 ]
39+
* - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
40+
* - val (0..7) [ 16 : 18 ]
41+
*
42+
* @param reg RCC_CFGRx register offset
43+
* @param shift Position within RCC_CFGRx.
44+
* @param mask Mask for the RCC_CFGRx field.
45+
* @param val Clock value (0, 1, ... 7).
46+
*/
47+
48+
#define STM32_CLOCK_REG_MASK 0xFFU
49+
#define STM32_CLOCK_REG_SHIFT 0U
50+
#define STM32_CLOCK_SHIFT_MASK 0x1FU
51+
#define STM32_CLOCK_SHIFT_SHIFT 8U
52+
#define STM32_CLOCK_MASK_MASK 0x7U
53+
#define STM32_CLOCK_MASK_SHIFT 13U
54+
#define STM32_CLOCK_VAL_MASK 0x7U
55+
#define STM32_CLOCK_VAL_SHIFT 16U
56+
57+
#define STM32_CLOCK(val, mask, shift, reg) \
58+
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
59+
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
60+
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
61+
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
62+
63+
/** @brief RCC_CFGRx register offset */
64+
#define CFGR3_REG 0x30
65+
66+
/** @brief Device clk sources selection helpers) */
67+
/** CFGR3 devices */
68+
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG)
69+
#define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG)
70+
#define I2C2_SEL(val) STM32_CLOCK(val, 1, 5, CFGR3_REG)
71+
#define I2C3_SEL(val) STM32_CLOCK(val, 1, 6, CFGR3_REG)
72+
#define TIM1_SEL(val) STM32_CLOCK(val, 1, 8, CFGR3_REG)
73+
#define TIM8_SEL(val) STM32_CLOCK(val, 1, 9, CFGR3_REG)
74+
#define TIM15_SEL(val) STM32_CLOCK(val, 1, 10, CFGR3_REG)
75+
#define TIM16_SEL(val) STM32_CLOCK(val, 1, 11, CFGR3_REG)
76+
#define TIM17_SEL(val) STM32_CLOCK(val, 1, 13, CFGR3_REG)
77+
#define TIM20_SEL(val) STM32_CLOCK(val, 1, 15, CFGR3_REG)
78+
#define USART2_SEL(val) STM32_CLOCK(val, 3, 16, CFGR3_REG)
79+
#define USART3_SEL(val) STM32_CLOCK(val, 3, 18, CFGR3_REG)
80+
#define USART4_SEL(val) STM32_CLOCK(val, 3, 20, CFGR3_REG)
81+
#define USART5_SEL(val) STM32_CLOCK(val, 3, 22, CFGR3_REG)
82+
#define TIM2_SEL(val) STM32_CLOCK(val, 1, 24, CFGR3_REG)
83+
#define TIM3_4_SEL(val) STM32_CLOCK(val, 1, 25, CFGR3_REG)
84+
85+
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */

‎include/zephyr/dt-bindings/clock/stm32g0_clock.h‎

Lines changed: 76 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,6 @@
66
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
77
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_
88

9-
/** Peripheral clock sources */
10-
119
/** Bus clocks */
1210
#define STM32_CLOCK_BUS_IOP 0x034
1311
#define STM32_CLOCK_BUS_AHB1 0x038
@@ -17,4 +15,80 @@
1715
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_IOP
1816
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
1917

18+
/** Peripheral clock sources */
19+
/* RM0444, §5.4.21/22 Clock configuration register (RCC_CCIPRx) */
20+
21+
/** Fixed clocks */
22+
#define STM32_SRC_HSI 0x001
23+
#define STM32_SRC_MSI 0x002
24+
#define STM32_SRC_LSE 0x003
25+
#define STM32_SRC_LSI 0x004
26+
/** System clock */
27+
#define STM32_SRC_SYSCLK 0x005
28+
/** Peripheral bus clock */
29+
#define STM32_SRC_PCLK 0x006
30+
/** PLL clock */
31+
#define STM32_SRC_PLLCLK 0x007
32+
33+
#define STM32_SRC_CLOCK_MIN STM32_SRC_HSI
34+
#define STM32_SRC_CLOCK_MAX STM32_SRC_PLLCLK
35+
36+
/**
37+
* @brief STM32 clock configuration bit field.
38+
*
39+
* - reg (1/2/3) [ 0 : 7 ]
40+
* - shift (0..31) [ 8 : 12 ]
41+
* - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
42+
* - val (0..7) [ 16 : 18 ]
43+
*
44+
* @param reg RCC_CCIPRx register offset
45+
* @param shift Position within RCC_CCIPRx.
46+
* @param mask Mask for the RCC_CCIPRx field.
47+
* @param val Clock value (0, 1, ... 7).
48+
*/
49+
50+
#define STM32_CLOCK_REG_MASK 0xFFU
51+
#define STM32_CLOCK_REG_SHIFT 0U
52+
#define STM32_CLOCK_SHIFT_MASK 0x1FU
53+
#define STM32_CLOCK_SHIFT_SHIFT 8U
54+
#define STM32_CLOCK_MASK_MASK 0x7U
55+
#define STM32_CLOCK_MASK_SHIFT 13U
56+
#define STM32_CLOCK_VAL_MASK 0x7U
57+
#define STM32_CLOCK_VAL_SHIFT 16U
58+
59+
#define STM32_CLOCK(val, mask, shift, reg) \
60+
((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
61+
(((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \
62+
(((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \
63+
(((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
64+
65+
/** @brief RCC_CCIPR register offset */
66+
#define CCIPR_REG 0x54
67+
#define CCIPR2_REG 0x58
68+
69+
/** @brief Device clk sources selection helpers */
70+
/** CCIPR devices */
71+
#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG)
72+
#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG)
73+
#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG)
74+
#define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CCIPR_REG)
75+
#define LPUART2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG)
76+
#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG)
77+
#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG)
78+
#define I2C2_I2S1_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG)
79+
#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG)
80+
#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG)
81+
#define TIM1_SEL(val) STM32_CLOCK(val, 1, 22, CCIPR_REG)
82+
#define TIM15_SEL(val) STM32_CLOCK(val, 1, 24, CCIPR_REG)
83+
#define RNG_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG)
84+
#define ADC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG)
85+
/** CCIPR2 devices */
86+
#define I2S1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR2_REG)
87+
#define I2S2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR2_REG)
88+
#define FDCAN_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR2_REG)
89+
#define USB_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG)
90+
91+
92+
93+
2094
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */

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