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14 | 14 | /** DCKCFGR devices */
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15 | 15 | #define CKDFSDM2A_SEL(val) STM32_CLOCK(val, 1, 14, DCKCFGR_REG)
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16 | 16 | #define CKDFSDM1A_SEL(val) STM32_CLOCK(val, 1, 15, DCKCFGR_REG)
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17 |
| -#define SAI1A_SEL(val) STM32_CLOCK(val, 2, 20, DCKCFGR_REG) |
18 |
| -#define SAI1B_SEL(val) STM32_CLOCK(val, 2, 22, DCKCFGR_REG) |
19 |
| -#define I2S1_SEL(val) STM32_CLOCK(val, 2, 25, DCKCFGR_REG) |
20 |
| -#define I2S2_SEL(val) STM32_CLOCK(val, 2, 27, DCKCFGR_REG) |
| 17 | +#define SAI1A_SEL(val) STM32_CLOCK(val, 3, 20, DCKCFGR_REG) |
| 18 | +#define SAI1B_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR_REG) |
| 19 | +#define I2S1_SEL(val) STM32_CLOCK(val, 3, 25, DCKCFGR_REG) |
| 20 | +#define I2S2_SEL(val) STM32_CLOCK(val, 3, 27, DCKCFGR_REG) |
21 | 21 | #define CKDFSDM_SEL(val) STM32_CLOCK(val, 1, 31, DCKCFGR_REG)
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22 | 22 |
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23 | 23 | /** DCKCFGR2 devices */
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24 |
| -#define I2CFMP1_SEL(val) STM32_CLOCK(val, 1, 22, DCKCFGR2_REG) |
| 24 | +#define I2CFMP1_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR2_REG) |
25 | 25 | #define CK48M_SEL(val) STM32_CLOCK(val, 1, 27, DCKCFGR2_REG)
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26 | 26 | #define SDIO_SEL(val) STM32_CLOCK(val, 1, 28, DCKCFGR2_REG)
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27 |
| -#define LPTIM1_SEL(val) STM32_CLOCK(val, 1, 30, DCKCFGR2_REG) |
| 27 | +#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 30, DCKCFGR2_REG) |
28 | 28 |
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29 | 29 | #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_ */
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