dts: stm32l4: Configure RNG domain clocks

Align RNG domain clock confguration on USB clock configuration.
For now we're not able to fully use CLK48 as a mux clock, so
this has to be done on both nodes rather than on a centralized
fashion.

Signed-off-by: Erwan Gouriou <[email protected]>

Author: erwango

dts/arm/st/l4/stm32l4.dtsi

@@ -405,7 +405,8 @@
 			compatible = "st,stm32-rng";
 			reg = <0x50060800 0x400>;
 			interrupts = <80 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
+				 <&rcc STM32_SRC_MSI CLK48_SEL(3)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/l4/stm32l496.dtsi

@@ -17,6 +17,11 @@
 			};
 		};
 
+		rng: rng@50060800 {
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
+				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
+		};
+
 		i2c4: i2c@40008400 {
 			compatible = "st,stm32-i2c-v2";
 			clock-frequency = <I2C_BITRATE_STANDARD>;

dts/arm/st/l4/stm32l4r5.dtsi

@@ -35,6 +35,11 @@
 			undershoot-prevention;
 		};
 
+		rng: rng@50060800 {
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
+				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
+		};
+
 		pinctrl: pin-controller@48000000 {
 			gpiod: gpio@48000c00 {
 				compatible = "st,stm32-gpio";