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lucien-nxpnashif
lucien-nxp
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nashif
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dts: arm: nxp: add dts files for RT1180
The offset of the peripheral is abstracted so that the peripheral can be defined in RT118x.dtsi,that is a common dtsi file for RT1180. Due to cm33 core, add ns/s files which are served on different status for cm33 core. Add rt118x_cm7 dtsi file Signed-off-by: Lucien Zhao <[email protected]>
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‎dts/arm/nxp/nxp_rt118x.dtsi

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <dt-bindings/clock/imx_ccm_rev2.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-m7";
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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};
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&peripheral {
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* Note that the offsets here are relative to the base address
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* defined in either nxp_rt118x_cm33_ns.dtsi, nxp_rt118x_cm33.dtsi
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* or nxp_rt118x_cm7.dtsi. The base addresses on cm33 core differ
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* between non-secure (0x40000000) and secure modes (0x50000000).
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*/
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iomuxc: iomuxc@2A10000 {
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compatible = "nxp,imx-iomuxc";
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reg = <0x2A10000 0x4000>;
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pinctrl: pinctrl {
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status = "okay";
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compatible = "nxp,mcux-rt11xx-pinctrl";
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};
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};
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iomuxc_aon: iomuxc@43C0000 {
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compatible = "nxp,mcux-rt-pinctrl";
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reg = <0x43C0000 0x4000>;
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status = "okay";
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};
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ccm: ccm@4450000 {
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compatible = "nxp,imx-ccm-rev2";
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reg = <0x4450000 0x4000>;
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#clock-cells = <3>;
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};
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lpuart1: uart@4380000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x4380000 0x4000>;
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interrupts = <19 0>;
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clocks = <&ccm IMX_CCM_LPUART0102_CLK 0x7c 24>;
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status = "disabled";
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};
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gpio1: gpio@7400000 {
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compatible = "nxp,imx-rgpio";
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reg = <0x7400000 0x4000>;
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interrupts = <10 0>, <11 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio4: gpio@3830000 {
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compatible = "nxp,imx-rgpio";
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reg = <0x3830000 0x4000>;
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interrupts = <232 0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&flexspi1 {
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compatible = "nxp,imx-flexspi";
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interrupts = <55 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0>;
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};

‎dts/arm/nxp/nxp_rt118x_cm33.dtsi

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <mem.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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/ {
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soc {
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itcm: itcm@1FFE0000 {
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compatible = "nxp,imx-itcm";
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reg = <0x1FFE0000 DT_SIZE_K(128)>;
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};
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dtcm: dtcm@30000000 {
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compatible = "nxp,imx-dtcm";
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reg = <0x30000000 DT_SIZE_K(128)>;
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};
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peripheral: peripheral@50000000 {
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ranges = <0x0 0x50000000 0x10000000>;
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};
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flexspi1: spi@525e0000 {
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reg = <0x525e0000 0x4000>,<0x38000000 DT_SIZE_M(128)>;
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};
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};
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};
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#include <nxp/nxp_rt118x.dtsi>
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/ {
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cpus {
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/delete-node/ cpu@1;
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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/*
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* GPIO pinmux options. These options define the pinmux settings
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* for GPIO ports on the package, so that the GPIO driver can
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* select GPIO mux options during GPIO configuration.
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*/
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&gpio1{
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pinmux = <&iomuxc_aon_gpio_aon_00_gpio1_io00>,
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<&iomuxc_aon_gpio_aon_01_gpio1_io01>,
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<&iomuxc_aon_gpio_aon_02_gpio1_io02>,
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<&iomuxc_aon_gpio_aon_03_gpio1_io03>,
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<&iomuxc_aon_gpio_aon_04_gpio1_io04>,
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<&iomuxc_aon_gpio_aon_05_gpio1_io05>,
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<&iomuxc_aon_gpio_aon_06_gpio1_io06>,
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<&iomuxc_aon_gpio_aon_07_gpio1_io07>,
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<&iomuxc_aon_gpio_aon_08_gpio1_io08>,
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<&iomuxc_aon_gpio_aon_09_gpio1_io09>,
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<&iomuxc_aon_gpio_aon_10_gpio1_io10>,
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<&iomuxc_aon_gpio_aon_11_gpio1_io11>,
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<&iomuxc_aon_gpio_aon_12_gpio1_io12>,
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<&iomuxc_aon_gpio_aon_13_gpio1_io13>,
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<&iomuxc_aon_gpio_aon_14_gpio1_io14>,
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<&iomuxc_aon_gpio_aon_15_gpio1_io15>,
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<&iomuxc_aon_gpio_aon_16_gpio1_io16>,
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<&iomuxc_aon_gpio_aon_17_gpio1_io17>,
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<&iomuxc_aon_gpio_aon_18_gpio1_io18>,
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<&iomuxc_aon_gpio_aon_19_gpio1_io19>,
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<&iomuxc_aon_gpio_aon_20_gpio1_io20>,
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<&iomuxc_aon_gpio_aon_21_gpio1_io21>,
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<&iomuxc_aon_gpio_aon_22_gpio1_io22>,
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<&iomuxc_aon_gpio_aon_23_gpio1_io23>,
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<&iomuxc_aon_gpio_aon_24_gpio1_io24>,
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<&iomuxc_aon_gpio_aon_25_gpio1_io25>,
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<&iomuxc_aon_gpio_aon_26_gpio1_io26>,
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<&iomuxc_aon_gpio_aon_27_gpio1_io27>;
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};
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&gpio4{
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pinmux = <&iomuxc_gpio_ad_00_gpio4_io00>,
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<&iomuxc_gpio_ad_01_gpio4_io01>,
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<&iomuxc_gpio_ad_02_gpio4_io02>,
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<&iomuxc_gpio_ad_03_gpio4_io03>,
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<&iomuxc_gpio_ad_04_gpio4_io04>,
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<&iomuxc_gpio_ad_05_gpio4_io05>,
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<&iomuxc_gpio_ad_06_gpio4_io06>,
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<&iomuxc_gpio_ad_07_gpio4_io07>,
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<&iomuxc_gpio_ad_08_gpio4_io08>,
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<&iomuxc_gpio_ad_09_gpio4_io09>,
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<&iomuxc_gpio_ad_10_gpio4_io10>,
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<&iomuxc_gpio_ad_11_gpio4_io11>,
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<&iomuxc_gpio_ad_12_gpio4_io12>,
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<&iomuxc_gpio_ad_13_gpio4_io13>,
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<&iomuxc_gpio_ad_14_gpio4_io14>,
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<&iomuxc_gpio_ad_15_gpio4_io15>,
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<&iomuxc_gpio_ad_16_gpio4_io16>,
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<&iomuxc_gpio_ad_17_gpio4_io17>,
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<&iomuxc_gpio_ad_18_gpio4_io18>,
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<&iomuxc_gpio_ad_19_gpio4_io19>,
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<&iomuxc_gpio_ad_20_gpio4_io20>,
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<&iomuxc_gpio_ad_21_gpio4_io21>,
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<&iomuxc_gpio_ad_22_gpio4_io22>,
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<&iomuxc_gpio_ad_23_gpio4_io23>,
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<&iomuxc_gpio_ad_24_gpio4_io24>,
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<&iomuxc_gpio_ad_25_gpio4_io25>,
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<&iomuxc_gpio_ad_26_gpio4_io26>,
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<&iomuxc_gpio_ad_27_gpio4_io27>,
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<&iomuxc_gpio_ad_28_gpio4_io28>,
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<&iomuxc_gpio_ad_29_gpio4_io29>,
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<&iomuxc_gpio_ad_30_gpio4_io30>,
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<&iomuxc_gpio_ad_31_gpio4_io31>;
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};

‎dts/arm/nxp/nxp_rt118x_cm33_ns.dtsi

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <mem.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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/ {
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soc {
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itcm: itcm@FFE0000 {
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compatible = "nxp,imx-itcm";
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reg = <0xFFE0000 DT_SIZE_K(128)>;
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};
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dtcm: dtcm@20000000 {
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compatible = "nxp,imx-dtcm";
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reg = <0x20000000 DT_SIZE_K(128)>;
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};
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peripheral: peripheral@40000000 {
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ranges = <0x0 0x40000000 0x10000000>;
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};
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flexspi1: spi@425e0000 {
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reg = <0x425e0000 0x4000>,<0x28000000 DT_SIZE_M(128)>;
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};
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};
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};
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#include <nxp/nxp_rt118x.dtsi>
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/ {
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cpus {
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/delete-node/ cpu@1;
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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/*
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* GPIO pinmux options. These options define the pinmux settings
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* for GPIO ports on the package, so that the GPIO driver can
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* select GPIO mux options during GPIO configuration.
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*/
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&gpio1{
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pinmux = <&iomuxc_aon_gpio_aon_00_gpio1_io00>,
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<&iomuxc_aon_gpio_aon_01_gpio1_io01>,
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<&iomuxc_aon_gpio_aon_02_gpio1_io02>,
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<&iomuxc_aon_gpio_aon_03_gpio1_io03>,
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<&iomuxc_aon_gpio_aon_04_gpio1_io04>,
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<&iomuxc_aon_gpio_aon_05_gpio1_io05>,
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<&iomuxc_aon_gpio_aon_06_gpio1_io06>,
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<&iomuxc_aon_gpio_aon_07_gpio1_io07>,
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<&iomuxc_aon_gpio_aon_08_gpio1_io08>,
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<&iomuxc_aon_gpio_aon_09_gpio1_io09>,
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<&iomuxc_aon_gpio_aon_10_gpio1_io10>,
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<&iomuxc_aon_gpio_aon_11_gpio1_io11>,
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<&iomuxc_aon_gpio_aon_12_gpio1_io12>,
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<&iomuxc_aon_gpio_aon_13_gpio1_io13>,
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<&iomuxc_aon_gpio_aon_14_gpio1_io14>,
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<&iomuxc_aon_gpio_aon_15_gpio1_io15>,
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<&iomuxc_aon_gpio_aon_16_gpio1_io16>,
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<&iomuxc_aon_gpio_aon_17_gpio1_io17>,
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<&iomuxc_aon_gpio_aon_18_gpio1_io18>,
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<&iomuxc_aon_gpio_aon_19_gpio1_io19>,
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<&iomuxc_aon_gpio_aon_20_gpio1_io20>,
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<&iomuxc_aon_gpio_aon_21_gpio1_io21>,
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<&iomuxc_aon_gpio_aon_22_gpio1_io22>,
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<&iomuxc_aon_gpio_aon_23_gpio1_io23>,
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<&iomuxc_aon_gpio_aon_24_gpio1_io24>,
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<&iomuxc_aon_gpio_aon_25_gpio1_io25>,
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<&iomuxc_aon_gpio_aon_26_gpio1_io26>,
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<&iomuxc_aon_gpio_aon_27_gpio1_io27>;
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};
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&gpio4{
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pinmux = <&iomuxc_gpio_ad_00_gpio4_io00>,
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<&iomuxc_gpio_ad_01_gpio4_io01>,
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<&iomuxc_gpio_ad_02_gpio4_io02>,
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<&iomuxc_gpio_ad_03_gpio4_io03>,
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<&iomuxc_gpio_ad_04_gpio4_io04>,
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<&iomuxc_gpio_ad_05_gpio4_io05>,
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<&iomuxc_gpio_ad_06_gpio4_io06>,
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<&iomuxc_gpio_ad_07_gpio4_io07>,
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<&iomuxc_gpio_ad_08_gpio4_io08>,
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<&iomuxc_gpio_ad_09_gpio4_io09>,
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<&iomuxc_gpio_ad_10_gpio4_io10>,
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<&iomuxc_gpio_ad_11_gpio4_io11>,
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<&iomuxc_gpio_ad_12_gpio4_io12>,
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<&iomuxc_gpio_ad_13_gpio4_io13>,
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<&iomuxc_gpio_ad_14_gpio4_io14>,
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<&iomuxc_gpio_ad_15_gpio4_io15>,
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<&iomuxc_gpio_ad_16_gpio4_io16>,
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<&iomuxc_gpio_ad_17_gpio4_io17>,
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<&iomuxc_gpio_ad_18_gpio4_io18>,
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<&iomuxc_gpio_ad_19_gpio4_io19>,
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<&iomuxc_gpio_ad_20_gpio4_io20>,
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<&iomuxc_gpio_ad_21_gpio4_io21>,
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<&iomuxc_gpio_ad_22_gpio4_io22>,
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<&iomuxc_gpio_ad_23_gpio4_io23>,
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<&iomuxc_gpio_ad_24_gpio4_io24>,
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<&iomuxc_gpio_ad_25_gpio4_io25>,
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<&iomuxc_gpio_ad_26_gpio4_io26>,
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<&iomuxc_gpio_ad_27_gpio4_io27>,
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<&iomuxc_gpio_ad_28_gpio4_io28>,
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<&iomuxc_gpio_ad_29_gpio4_io29>,
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<&iomuxc_gpio_ad_30_gpio4_io30>,
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<&iomuxc_gpio_ad_31_gpio4_io31>;
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};

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