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soc: mimxrt798s/hifi4: Add soc.c
Add soc.c. Handle IRQ mapping (INPUTMUX) and clock setup. Signed-off-by: Vit Stanicek <[email protected]>
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‎soc/nxp/imxrt/imxrt6xx/hifi4/soc.c

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__weak void mimxrt685s_hifi4_irq_init(void)
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{
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/**
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/*
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* IRQ assignments
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*
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* L1: (lowest priority)

‎soc/nxp/imxrt/imxrt7xx/hifi4/CMakeLists.txt

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zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include)
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zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR})
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zephyr_sources(soc.c)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

‎soc/nxp/imxrt/imxrt7xx/hifi4/soc.c

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/*
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* Copyright 2024-2025 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/devicetree.h>
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#include <fsl_clock.h>
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#include <fsl_inputmux.h>
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(edma1), okay)
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#define SYSCON_BASE DT_REG_ADDR(DT_NODELABEL(syscon0))
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#define EN_NUM 4
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#define EDMA_EN_OFFSET 0x420
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#define EDMA_EN_REG(instance, idx) ((uint32_t *)((uint32_t)(SYSCON_BASE) + \
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(EDMA_EN_OFFSET) + 0x10U * (instance) + 4U * (idx)))
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#endif
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#define SET_UP_FLEXCOMM_CLOCK(x) \
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do { \
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CLOCK_AttachClk(kFCCLK0_to_FLEXCOMM##x); \
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RESET_ClearPeripheralReset(kFC##x##_RST_SHIFT_RSTn); \
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CLOCK_EnableClock(kCLOCK_LPFlexComm##x); \
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} while (0)
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#if CONFIG_DT_HAS_NXP_MCUX_EDMA_ENABLED
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static void edma_enable_all_request(uint8_t instance)
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{
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uint32_t *reg;
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for (uint8_t idx = 0; idx < EN_NUM; idx++) {
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reg = EDMA_EN_REG(instance, idx);
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*reg |= 0xFFFFFFFFU;
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}
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}
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#endif
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__weak void mimxrt798s_hifi4_irq_init(void)
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{
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/**
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* IRQ assignments
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*
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* NMI:
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* - IRQ 0 (SEL 0): Yet unassigned
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*
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* L1: (lowest priority)
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* - IRQ 6 (SEL 1): FLEXCOMM0
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* - IRQ 7 (SEL 2): FLEXCOMM2
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* - IRQ 8 (SEL 3): WWDT1
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* - IRQ 9 (SEL 4): PINT0
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* - IRQ 10 (SEL 5): PINT1
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* - IRQ 11 (SEL 6): PINT2
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* - IRQ 12 (SEL 7): PINT3
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* - IRQ 13 (SEL 8): PINT4
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* - IRQ 14 (SEL 9): PINT5
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* - IRQ 15 (SEL 10): PINT6
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*
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* L2:
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* - IRQ 16 (SEL 11): PINT7
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* - IRQ 17 (SEL 12): LPSPI14
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* - IRQ 18 (SEL 13): MU2
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* - IRQ 19 (SEL 14): MU4
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* - IRQ 20 (SEL 15): EDMA1-0
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* - IRQ 21 (SEL 16): EDMA1-1
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* - IRQ 22 (SEL 17): EDMA1-2
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* - IRQ 23 (SEL 18): EDMA1-3
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*
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* L3: (highest priority)
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* - IRQ 24 (SEL 19): EDMA1-4
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* - IRQ 25 (SEL 20): EDMA1-5
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* - IRQ 26 (SEL 21): EDMA1-6
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* - IRQ 27 (SEL 22): EDMA1-7
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* - IRQ 28 (SEL 23): MICFIL
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* - IRQ 29 (SEL 24): SAI0
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* - IRQ 30 (SEL 25): SAI1
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* - IRQ 31 (SEL 26): SAI2
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*/
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INPUTMUX_Init(INPUTMUX0);
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INPUTMUX_AttachSignal(INPUTMUX0, 1, kINPUTMUX_Flexcomm0ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 2, kINPUTMUX_Flexcomm2ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 3, kINPUTMUX_Wdt1ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 4, kINPUTMUX_Gpio0Irq0ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 5, kINPUTMUX_Gpio0Irq1ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 6, kINPUTMUX_GpioInt2ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 7, kINPUTMUX_GpioInt3ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 8, kINPUTMUX_GpioInt4ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 9, kINPUTMUX_GpioInt5ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 10, kINPUTMUX_GpioInt6ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 11, kINPUTMUX_GpioInt7ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 12, kINPUTMUX_Spi14ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 13, kINPUTMUX_Mu2AToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 14, kINPUTMUX_Mu4BToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 15, kINPUTMUX_Dma1Irq0ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 16, kINPUTMUX_Dma1Irq1ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 17, kINPUTMUX_Dma1Irq2ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 18, kINPUTMUX_Dma1Irq3ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 19, kINPUTMUX_Dma1Irq4ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 20, kINPUTMUX_Dma1Irq5ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 21, kINPUTMUX_Dma1Irq6ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 22, kINPUTMUX_Dma1Irq7ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 23, kINPUTMUX_MicfilToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 24, kINPUTMUX_Sai0ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 25, kINPUTMUX_Sai1ToDspInterrupt);
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INPUTMUX_AttachSignal(INPUTMUX0, 26, kINPUTMUX_Sai2ToDspInterrupt);
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INPUTMUX_Deinit(INPUTMUX0);
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}
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__weak void mimxrt798s_hifi4_clock_init(void)
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{
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CLOCK_AttachClk(kOSC_CLK_to_FCCLK0);
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CLOCK_SetClkDiv(kCLOCK_DivFcclk0Clk, 1U);
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm0), okay)
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SET_UP_FLEXCOMM_CLOCK(0);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm2), okay)
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SET_UP_FLEXCOMM_CLOCK(2);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(edma1), okay)
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CLOCK_EnableClock(kCLOCK_Dma1);
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RESET_ClearPeripheralReset(kDMA1_RST_SHIFT_RSTn);
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edma_enable_all_request(1);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(sai0), okay)
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/* SAI clock 368.64 / 15 = 24.576MHz */
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CLOCK_AttachClk(kAUDIO_PLL_PFD3_to_AUDIO_VDD2);
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CLOCK_AttachClk(kAUDIO_VDD2_to_SAI012);
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CLOCK_SetClkDiv(kCLOCK_DivSai012Clk, 15U);
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RESET_ClearPeripheralReset(kSAI0_RST_SHIFT_RSTn);
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#endif
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}
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void soc_early_init_hook(void)
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{
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mimxrt798s_hifi4_irq_init();
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mimxrt798s_hifi4_clock_init();
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}

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