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nhutnguyenkc
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drivers: gpio: Add support for RZ/T2L
Add GPIO driver support for RZ/T2L Signed-off-by: Nhut Nguyen <[email protected]> Signed-off-by: Hieu Nguyen <[email protected]>
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4 files changed

+360
-53
lines changed

4 files changed

+360
-53
lines changed

‎drivers/gpio/gpio_renesas_rz.c‎

Lines changed: 58 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
#include <zephyr/drivers/gpio/gpio_utils.h>
1616
#include "gpio_renesas_rz.h"
1717
#include <zephyr/logging/log.h>
18-
#if defined(CONFIG_SOC_SERIES_RZN2L)
18+
#if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
1919
#include "r_icu.h"
2020
#include <zephyr/drivers/interrupt_controller/intc_rz_ext_irq.h>
2121
#endif
@@ -33,7 +33,7 @@ struct gpio_rz_config {
3333
const ioport_api_t *fsp_api;
3434
const struct device *int_dev;
3535
uint8_t int_num[GPIO_RZ_MAX_INT_NUM];
36-
#if defined(CONFIG_SOC_SERIES_RZN2L)
36+
#if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
3737
const struct device *eirq_dev[GPIO_RZ_MAX_INT_NUM];
3838

3939
void (*cb_list[GPIO_RZ_MAX_INT_NUM])(void *arg);
@@ -45,7 +45,7 @@ struct gpio_rz_data {
4545
sys_slist_t cb;
4646
ioport_instance_ctrl_t *fsp_ctrl;
4747
struct k_spinlock lock;
48-
#if defined(CONFIG_SOC_SERIES_RZN2L)
48+
#if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
4949
uint8_t pin[GPIO_RZ_MAX_INT_NUM];
5050
#endif
5151
};
@@ -60,44 +60,59 @@ struct gpio_rz_int_data {
6060
uint32_t irq_set_edge;
6161
};
6262

63+
struct gpio_rz_hw_config {
64+
gpio_flags_t p_pm;
65+
uint8_t pfc;
66+
};
67+
6368
struct gpio_rz_tint_config {
6469
void (*gpio_int_init)(void);
6570
};
6671

67-
static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, uint32_t *flags);
72+
static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, struct gpio_rz_hw_config *flags);
6873

6974
#ifdef CONFIG_GPIO_GET_CONFIG
7075
static int gpio_rz_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags)
7176
{
7277
const struct gpio_rz_config *config = dev->config;
7378
bsp_io_port_pin_t port_pin = config->fsp_port | pin;
79+
struct gpio_rz_hw_config hw_flags;
80+
81+
gpio_rz_pin_config_get_raw(port_pin, &hw_flags);
82+
*flags = hw_flags.p_pm;
7483

75-
gpio_rz_pin_config_get_raw(port_pin, flags);
7684
return 0;
7785
}
7886
#endif
7987

8088
/* Get previous pin's configuration, used by pin_configure/pin_interrupt_configure api */
81-
static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, uint32_t *flags)
89+
static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, struct gpio_rz_hw_config *flags)
8290
{
8391
bsp_io_port_t port = (port_pin >> 8U) & 0xFF;
8492
gpio_pin_t pin = port_pin & 0xFF;
8593
volatile uint8_t *p_p = GPIO_RZ_IOPORT_P_REG_GET(port, pin);
8694
volatile uint16_t *p_pm = GPIO_RZ_IOPORT_PM_REG_GET(port, pin);
95+
volatile uint32_t *p_pfc = GPIO_RZ_IOPORT_PFC_REG_GET(port, pin);
8796

8897
uint8_t p_value;
8998
uint16_t pm_value;
99+
uint32_t pfc_value;
90100

91101
p_value = GPIO_RZ_P_VALUE_GET(*p_p, pin);
92102
pm_value = GPIO_RZ_PM_VALUE_GET(*p_pm, pin);
103+
pfc_value = GPIO_RZ_PFC_VALUE_GET(*p_pfc, pin);
104+
105+
flags->p_pm = 0;
106+
flags->pfc = 0;
93107

94108
if (p_value) {
95-
*flags |= GPIO_OUTPUT_INIT_HIGH;
109+
flags->p_pm |= GPIO_OUTPUT_INIT_HIGH;
96110
} else {
97-
*flags |= GPIO_OUTPUT_INIT_LOW;
111+
flags->p_pm |= GPIO_OUTPUT_INIT_LOW;
98112
}
99113

100-
*flags |= ((pm_value << 16));
114+
flags->p_pm |= (pm_value << 16);
115+
flags->pfc |= pfc_value;
101116
return 0;
102117
}
103118

@@ -107,18 +122,14 @@ static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_
107122
struct gpio_rz_data *data = dev->data;
108123
bsp_io_port_pin_t port_pin = config->fsp_port | pin;
109124
uint32_t ioport_config_data = 0;
110-
gpio_flags_t pre_flags;
125+
struct gpio_rz_hw_config pre_flags;
111126
fsp_err_t err;
112127

113128
gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
114129

115130
if (!flags) {
116131
/* Disconnect mode */
117-
#if defined(CONFIG_SOC_SERIES_RZN2L)
118132
GPIO_RZ_PIN_DISCONNECT(config->fsp_port, pin);
119-
#elif defined(CONFIG_SOC_SERIES_RZG3S)
120-
ioport_config_data = 0;
121-
#endif /* CONFIG_SOC_SERIES_* */
122133
} else if (!(flags & GPIO_OPEN_DRAIN)) {
123134
/* PM register */
124135
ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET;
@@ -134,7 +145,7 @@ static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_
134145
}
135146
/* P register */
136147
if (!(flags & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW))) {
137-
flags |= pre_flags & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW);
148+
flags |= pre_flags.p_pm & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW);
138149
}
139150

140151
if (flags & GPIO_OUTPUT_INIT_HIGH) {
@@ -149,22 +160,33 @@ static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_
149160
ioport_config_data |= IOPORT_CFG_PULLDOWN_ENABLE;
150161
}
151162

152-
/* ISEL register */
163+
/*
164+
* Interrupt register
165+
* RZG: ISEL
166+
* RZTN: PMC
167+
*/
153168
if (flags & GPIO_INT_ENABLE) {
154169
ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_INT_ENABLE;
155170
} else if (flags & GPIO_INT_DISABLE) {
156171
ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INT_DISABLE;
157172
}
158173

159-
/* Drive Ability register */
174+
/*
175+
* Drive ability register
176+
* RZG: IOLH
177+
* RZTN: DRCTL
178+
*/
160179
ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET(flags);
161-
#if defined(CONFIG_SOC_SERIES_RZG3S)
162-
/* Filter register, see in renesas-rz-gpio-ioport.h */
163-
ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flags);
164-
#elif defined(CONFIG_SOC_SERIES_RZN2L)
165-
/* RSEL reg */
166-
ioport_config_data |= IOPORT_CFG_REGION_NSAFETY;
167-
#endif /* CONFIG_SOC_SERIES_* */
180+
181+
/* PFC register */
182+
ioport_config_data |= GPIO_RZ_IOPORT_PFC_SET(pre_flags.pfc);
183+
184+
/*
185+
* Specific register
186+
* RZG: FILONOFF, FILNUM, FILCLKSEL
187+
* RZTN: RSELP
188+
*/
189+
ioport_config_data |= GPIO_RZ_PIN_SPECIAL_FLAG_GET(flags);
168190
} else {
169191
return -ENOTSUP;
170192
}
@@ -242,17 +264,17 @@ static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t p
242264
const struct gpio_rz_config *config = dev->config;
243265
struct gpio_rz_data *data = dev->data;
244266
bsp_io_port_pin_t port_pin;
245-
gpio_flags_t pre_flags;
267+
struct gpio_rz_hw_config pre_flags;
246268
ioport_size_t value = 0;
247269
fsp_err_t err;
248270

249271
for (uint8_t idx = 0; idx < config->ngpios; idx++) {
250272
if (pins & (1U << idx)) {
251273
port_pin = config->fsp_port | idx;
252274
gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
253-
if (pre_flags & GPIO_OUTPUT_INIT_HIGH) {
275+
if (pre_flags.p_pm & GPIO_OUTPUT_INIT_HIGH) {
254276
value &= (1U << idx);
255-
} else if (pre_flags & GPIO_OUTPUT_INIT_LOW) {
277+
} else if (pre_flags.p_pm & GPIO_OUTPUT_INIT_LOW) {
256278
value |= (1U << idx);
257279
}
258280
}
@@ -297,7 +319,7 @@ static int gpio_rz_int_disable(const struct device *dev, const struct device *gp
297319

298320
data->gpio_mapping[int_num].gpio_dev = NULL;
299321
data->gpio_mapping[int_num].pin = UINT8_MAX;
300-
#elif defined(CONFIG_SOC_SERIES_RZN2L)
322+
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
301323
const struct gpio_rz_config *gpio_config = gpio_dev->config;
302324
const struct device *eirq_dev = gpio_config->eirq_dev[pin];
303325

@@ -339,7 +361,7 @@ static int gpio_rz_int_enable(const struct device *int_dev, const struct device
339361
irq_enable(GPIO_RZ_TINT_IRQ_GET(int_num));
340362
int_data->gpio_mapping[int_num].gpio_dev = gpio_dev;
341363
int_data->gpio_mapping[int_num].pin = pin;
342-
#elif defined(CONFIG_SOC_SERIES_RZN2L)
364+
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
343365
const struct device *eirq_dev = gpio_config->eirq_dev[pin];
344366
struct gpio_rz_data *gpio_data = gpio_dev->data;
345367

@@ -363,7 +385,7 @@ static int gpio_rz_pin_interrupt_configure(const struct device *dev, gpio_pin_t
363385
bsp_io_port_pin_t port_pin = config->fsp_port | pin;
364386
uint8_t int_num = config->int_num[pin];
365387
uint8_t irq_type = 0;
366-
gpio_flags_t pre_flags = 0;
388+
struct gpio_rz_hw_config pre_flags;
367389
k_spinlock_key_t key;
368390
int ret = 0;
369391

@@ -379,8 +401,8 @@ static int gpio_rz_pin_interrupt_configure(const struct device *dev, gpio_pin_t
379401

380402
if (mode == GPIO_INT_MODE_DISABLED) {
381403
gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
382-
pre_flags |= GPIO_INT_DISABLE;
383-
gpio_rz_pin_configure(dev, pin, pre_flags);
404+
pre_flags.p_pm |= GPIO_INT_DISABLE;
405+
gpio_rz_pin_configure(dev, pin, pre_flags.p_pm);
384406
gpio_rz_int_disable(config->int_dev, dev, int_num, pin);
385407
goto exit_unlock;
386408
}
@@ -404,8 +426,8 @@ static int gpio_rz_pin_interrupt_configure(const struct device *dev, gpio_pin_t
404426
ret = gpio_rz_int_enable(config->int_dev, dev, int_num, irq_type, pin);
405427
if (ret == 0) {
406428
gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
407-
pre_flags |= GPIO_INT_ENABLE;
408-
gpio_rz_pin_configure(dev, pin, pre_flags);
429+
pre_flags.p_pm |= GPIO_INT_ENABLE;
430+
gpio_rz_pin_configure(dev, pin, pre_flags.p_pm);
409431
}
410432

411433
exit_unlock:
@@ -442,7 +464,7 @@ static void gpio_rz_isr(uint16_t irq, void *param)
442464
struct gpio_rz_data *gpio_data = gpio_dev->data;
443465

444466
gpio_fire_callbacks(&gpio_data->cb, gpio_dev, BIT(pin));
445-
#elif defined(CONFIG_SOC_SERIES_RZN2L)
467+
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
446468
const struct device *gpio_dev = (const struct device *)param;
447469
struct gpio_rz_data *gpio_data = gpio_dev->data;
448470
uint8_t pin = gpio_data->pin[irq];
@@ -515,7 +537,7 @@ static int gpio_rz_int_init(const struct device *dev)
515537
UTIL_DEC(CONFIG_GPIO_INIT_PRIORITY), NULL);
516538
DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT)
517539

518-
#elif defined(CONFIG_SOC_SERIES_RZN2L) && GPIO_RZ_HAS_INTERRUPT
540+
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) && GPIO_RZ_HAS_INTERRUPT
519541

520542
GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM)
521543

‎drivers/gpio/gpio_renesas_rz.h‎

Lines changed: 33 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -14,14 +14,21 @@
1414
#if defined(CONFIG_SOC_SERIES_RZG3S)
1515
#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
1616

17-
#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P_20)
18-
#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM_20)
17+
#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P_20)
18+
#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM_20)
19+
#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET (&R_GPIO->PFC_20)
1920

20-
#define GPIO_RZ_IOPORT_P_REG_GET(port, pin) (&GPIO_RZ_IOPORT_P_REG_BASE_GET[port + (pin / 4)])
21-
#define GPIO_RZ_IOPORT_PM_REG_GET(port, pin) (&GPIO_RZ_IOPORT_PM_REG_BASE_GET[port + (pin / 4)])
21+
#define GPIO_RZ_IOPORT_P_REG_GET(port, pin) (&GPIO_RZ_IOPORT_P_REG_BASE_GET[port + (pin / 4)])
22+
#define GPIO_RZ_IOPORT_PM_REG_GET(port, pin) (&GPIO_RZ_IOPORT_PM_REG_BASE_GET[port + (pin / 4)])
23+
#define GPIO_RZ_IOPORT_PFC_REG_GET(port, pin) (&GPIO_RZ_IOPORT_PFC_REG_BASE_GET[port + (pin / 4)])
2224

23-
#define GPIO_RZ_P_VALUE_GET(value, pin) ((value >> pin) & 1U)
24-
#define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U)
25+
#define GPIO_RZ_P_VALUE_GET(value, pin) ((value >> pin) & 1U)
26+
#define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U)
27+
#define GPIO_RZ_PFC_VALUE_GET(value, pin) ((value >> (pin * 4)) & 0xF)
28+
29+
#define GPIO_RZ_IOPORT_PFC_SET(value) (value << 24)
30+
31+
#define GPIO_RZ_PIN_DISCONNECT(port, pin) /* do nothing */
2532

2633
#define GPIO_RZ_MAX_PORT_NUM 19
2734
#define GPIO_RZ_MAX_INT_NUM 32
@@ -45,28 +52,36 @@
4552
#define GPIO_RZ_PIN_CONFIGURE_INT_ENABLE IOPORT_CFG_TINT_ENABLE
4653
#define GPIO_RZ_PIN_CONFIGURE_INT_DISABLE (~(IOPORT_CFG_TINT_ENABLE))
4754
#define GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET (~(0x3 << 2))
55+
#define GPIO_RZ_PIN_SPECIAL_FLAG_GET(flag) GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag)
4856

4957
static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43,
5058
47, 52, 56, 58, 63, 66, 70, 72, 76};
5159

52-
#elif defined(CONFIG_SOC_SERIES_RZN2L)
60+
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
5361
#include <zephyr/dt-bindings/gpio/renesas-rztn-gpio.h>
54-
#define GPIO_RZ_IOPORT_P_REG_REGION_GET(p) (R_BSP_IoRegionGet(p) == BSP_IO_REGION_NOT_SAFE ? 1 : 0)
55-
#define GPIO_RZ_IOPORT_PM_REG_REGION_GET(p) (R_BSP_IoRegionGet(p) == BSP_IO_REGION_NOT_SAFE ? 1 : 0)
62+
#define GPIO_RZ_IOPORT_REG_REGION_GET(p) (R_BSP_IoRegionGet(p) == BSP_IO_REGION_NOT_SAFE ? 1 : 0)
5663

5764
#define GPIO_RZ_IOPORT_P_REG_BASE_GET(port, pin) \
58-
(GPIO_RZ_IOPORT_P_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->P[port] \
59-
: &R_PORT_SR->P[port])
65+
(GPIO_RZ_IOPORT_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->P[port] \
66+
: &R_PORT_SR->P[port])
6067

6168
#define GPIO_RZ_IOPORT_PM_REG_BASE_GET(port, pin) \
62-
(GPIO_RZ_IOPORT_PM_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->PM[port] \
63-
: &R_PORT_SR->PM[port])
69+
(GPIO_RZ_IOPORT_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->PM[port] \
70+
: &R_PORT_SR->PM[port])
71+
72+
#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET(port, pin) \
73+
(GPIO_RZ_IOPORT_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->PFC[port] \
74+
: &R_PORT_SR->PFC[port])
75+
76+
#define GPIO_RZ_IOPORT_P_REG_GET(port, pin) (GPIO_RZ_IOPORT_P_REG_BASE_GET(port, pin))
77+
#define GPIO_RZ_IOPORT_PM_REG_GET(port, pin) (GPIO_RZ_IOPORT_PM_REG_BASE_GET(port, pin))
78+
#define GPIO_RZ_IOPORT_PFC_REG_GET(port, pin) (GPIO_RZ_IOPORT_PFC_REG_BASE_GET(port, pin))
6479

65-
#define GPIO_RZ_IOPORT_P_REG_GET(port, pin) (GPIO_RZ_IOPORT_P_REG_BASE_GET(port, pin))
66-
#define GPIO_RZ_IOPORT_PM_REG_GET(port, pin) (GPIO_RZ_IOPORT_PM_REG_BASE_GET(port, pin))
80+
#define GPIO_RZ_P_VALUE_GET(value, pin) ((value >> pin) & 1U)
81+
#define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U)
82+
#define GPIO_RZ_PFC_VALUE_GET(value, pin) ((value >> (pin * 4)) & 0xF)
6783

68-
#define GPIO_RZ_P_VALUE_GET(value, pin) ((value >> pin) & 1U)
69-
#define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U)
84+
#define GPIO_RZ_IOPORT_PFC_SET(value) (value << 4)
7085

7186
#define GPIO_RZ_PIN_DISCONNECT(port, pin) \
7287
*GPIO_RZ_IOPORT_PM_REG_GET((port >> 8U), pin) &= ~(3U << (pin * 2))
@@ -84,6 +99,7 @@ static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23
8499
#define GPIO_RZ_PIN_CONFIGURE_INT_ENABLE (1U << 3)
85100
#define GPIO_RZ_PIN_CONFIGURE_INT_DISABLE (~(1U << 3))
86101
#define GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET (~(0x3 << 2))
102+
#define GPIO_RZ_PIN_SPECIAL_FLAG_GET(flag) IOPORT_CFG_REGION_NSAFETY
87103

88104
#endif /* CONFIG_SOC_* */
89105

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