driver: interrupt_controller: intc_clic: rework to standard CLIC driver

Rework intc_clic to standard CLIC driver with Nuclei ECLIC extention.

Signed-off-by: Jimmy Zheng <[email protected]>

Author: jimmyzhe

drivers/interrupt_controller/CMakeLists.txt

@@ -31,8 +31,8 @@ zephyr_library_sources_ifdef(CONFIG_INTC_ESP32              intc_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_SWERV_PIC               intc_swerv_pic.c)
 zephyr_library_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ      intc_vexriscv_litex.c)
 zephyr_library_sources_ifdef(CONFIG_VIM                     intc_vim.c)
-zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC            intc_clic.c)
-zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC            intc_clic.S)
+zephyr_library_sources_ifdef(CONFIG_CLIC                    intc_clic.c)
+zephyr_library_sources_ifdef(CONFIG_CLIC                    intc_clic.S)
 zephyr_library_sources_ifdef(CONFIG_NRFX_CLIC               intc_nrfx_clic.c)
 zephyr_library_sources_ifdef(CONFIG_NRFX_CLIC               intc_nrfx_clic.S)
 zephyr_library_sources_ifdef(CONFIG_NXP_S32_EIRQ            intc_eirq_nxp_s32.c)

drivers/interrupt_controller/Kconfig.clic

@@ -1,11 +1,20 @@
 # Copyright (c) 2021 Tokita, Hiroshi <[email protected]>
 # SPDX-License-Identifier: Apache-2.0
 
+config CLIC
+	bool "RISC-V Core Local Interrupt Controller (CLIC)"
+	default y
+	depends on DT_HAS_NUCLEI_ECLIC_ENABLED || DT_HAS_RISCV_CLIC_ENABLED
+	select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
+	help
+	  Core Local Interrupt Controller provide low-latency, vectored,
+	  preemptive interrupts for RISC-V systems.
+
 config NUCLEI_ECLIC
 	bool "Enhanced Core Local Interrupt Controller (ECLIC)"
 	default y
 	depends on DT_HAS_NUCLEI_ECLIC_ENABLED
-	select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
+	select CLIC
 	select CLIC_SMCLICSHV_EXT if RISCV_VECTORED_MODE
 	help
 	  Interrupt controller for Nuclei SoC core.
@@ -18,20 +27,20 @@ config NRFX_CLIC
 	help
 	  Interrupt controller for Nordic VPR cores.
 
+if CLIC
+
 config CLIC_SMCLICSHV_EXT
 	bool
 	help
 	  The selective hardware vectoring extension gives users the flexibility
 	  to select the behavior for each interrupt. The CLIC driver needs to
 	  implement the riscv_clic_irq_vector_set() function.
 
-if NUCLEI_ECLIC
-
 config LEGACY_CLIC
 	bool "Use the legacy clic specification"
 	depends on RISCV_HAS_CLIC
 	help
 	  Enables legacy clic, where smclicshv extension is not supported and
 	  hardware vectoring is set via mode bits of mtvec.
 
-endif # NUCLEI_ECLIC
+endif # CLIC

drivers/interrupt_controller/intc_clic.S

@@ -5,15 +5,16 @@
  */
 
 /**
- * @brief Assembler-hooks specific to Nuclei's Extended Core Interrupt Controller
+ * @brief Assembler-hooks specific to RISC-V Core Local Interrupt Controller
  */
 
 #include <zephyr/arch/cpu.h>
+#include "intc_clic.h"
 
 
 GTEXT(__soc_handle_irq)
 /*
- * In an ECLIC, pending interrupts don't have to be cleared by hand.
+ * In an CLIC, pending interrupts don't have to be cleared by hand.
  * In vectored mode, interrupts are cleared automatically.
  * In non-vectored mode, interrupts are cleared when writing the mnxti register (done in
  * __soc_handle_all_irqs).
@@ -31,15 +32,15 @@ GTEXT(sys_trace_isr_exit)
 #endif
 
 /*
- * This function services and clears all pending interrupts for an ECLIC in non-vectored mode.
+ * This function services and clears all pending interrupts for an CLIC in non-vectored mode.
  */
 SECTION_FUNC(exception.other, __soc_handle_all_irqs)
 	addi sp, sp, -16
 	sw ra, 0(sp)
 
 	/* Read and clear mnxti to get highest current interrupt and enable interrupts. Will return
 	 * original interrupt if no others appear. */
-	csrrci a0, 0x345, MSTATUS_IEN
+	csrrci a0, CSR_MNXTI, MSTATUS_IEN
 	beqz a0, irq_done /* Check if original interrupt vanished. */
 
 irq_loop:
@@ -50,7 +51,7 @@ irq_loop:
 
 	/* Call corresponding registered function in _sw_isr_table. a0 is offset in pointer with
 	 * the mtvt, sw irq table is 2-pointer wide -> shift by one. */
-	csrr t0, 0x307 /* mtvt */
+	csrr t0, CSR_MTVT
 	sub a0, a0, t0
 	la t0, _sw_isr_table
 	slli a0, a0, (1)
@@ -70,7 +71,7 @@ irq_loop:
 #endif
 
 	/* Read and clear mnxti to get highest current interrupt and enable interrupts. */
-	csrrci a0, 0x345, MSTATUS_IEN
+	csrrci a0, CSR_MNXTI, MSTATUS_IEN
 	bnez a0, irq_loop
 
 irq_done:

drivers/interrupt_controller/intc_clic.c

@@ -1,129 +1,186 @@
 /*
  * Copyright (c) 2021 Tokita, Hiroshi <[email protected]>
+ * Copyright (c) 2025 Andes Technology Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 /**
- * @brief Driver for Nuclie's Extended Core Interrupt Controller
+ * @brief Driver for Core Local Interrupt Controller
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/arch/cpu.h>
-#include <zephyr/sys/util.h>
+#include <zephyr/arch/riscv/csr.h>
 #include <zephyr/device.h>
-
-#include <zephyr/sw_isr_table.h>
 #include <zephyr/drivers/interrupt_controller/riscv_clic.h>
 #include "intc_clic.h"
 
+#if DT_HAS_COMPAT_STATUS_OKAY(riscv_clic)
+#define DT_DRV_COMPAT riscv_clic
+#elif DT_HAS_COMPAT_STATUS_OKAY(nuclei_eclic)
 #define DT_DRV_COMPAT nuclei_eclic
+#else
+#error "Unknown CLIC controller compatible for this configuration"
+#endif
 
-/** CLIC INTATTR: TRIG Mask */
-#define CLIC_INTATTR_TRIG_Msk  0x3U
-
-#define ECLIC_CFG       (*((volatile union CLICCFG  *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 0))))
-#define ECLIC_INFO      (*((volatile union CLICINFO *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 1))))
-#define ECLIC_MTH       (*((volatile union CLICMTH  *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 2))))
-#define ECLIC_CTRL      ((volatile  struct CLICCTRL *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 3)))
-#define ECLIC_CTRL_SIZE (DT_REG_SIZE_BY_IDX(DT_NODELABEL(eclic), 3))
+struct clic_data {
+	uint8_t nlbits;
+	uint8_t intctlbits;
+};
 
-static uint8_t nlbits;
-static uint8_t intctlbits;
-static uint8_t max_prio;
-static uint8_t max_level;
-static uint8_t intctrl_mask;
-
-static inline uint8_t leftalign8(uint8_t val, uint8_t shift)
-{
-	return (val << (8U - shift));
-}
-
-static inline uint8_t mask8(uint8_t len)
-{
-	return ((1 << len) - 1) & 0xFFFFU;
-}
+struct clic_config {
+	mem_addr_t base;
+};
 
 /**
  * @brief Enable interrupt
  */
 void riscv_clic_irq_enable(uint32_t irq)
 {
-	ECLIC_CTRL[irq].INTIE.b.IE = 1;
+	const struct device *dev = DEVICE_DT_INST_GET(0);
+	const struct clic_config *config = dev->config;
+	union CLICINTIE clicintie = {.b = {.IE = 0x1}};
+
+	sys_write8(clicintie.w, config->base + CLIC_INTIE(irq));
 }
 
 /**
  * @brief Disable interrupt
  */
 void riscv_clic_irq_disable(uint32_t irq)
 {
-	ECLIC_CTRL[irq].INTIE.b.IE = 0;
+	const struct device *dev = DEVICE_DT_INST_GET(0);
+	const struct clic_config *config = dev->config;
+	union CLICINTIE clicintie = {.b = {.IE = 0x0}};
+
+	sys_write8(clicintie.w, config->base + CLIC_INTIE(irq));
 }
 
 /**
  * @brief Get enable status of interrupt
  */
 int riscv_clic_irq_is_enabled(uint32_t irq)
 {
-	return ECLIC_CTRL[irq].INTIE.b.IE;
+	const struct device *dev = DEVICE_DT_INST_GET(0);
+	const struct clic_config *config = dev->config;
+	union CLICINTIE clicintie = {.w = sys_read8(config->base + CLIC_INTIE(irq))};
+
+	return clicintie.b.IE;
 }
 
 /**
  * @brief Set priority and level of interrupt
  */
 void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags)
 {
-	const uint8_t prio = leftalign8(MIN(pri, max_prio), intctlbits);
-	const uint8_t level =  leftalign8(max_level, nlbits);
-	const uint8_t intctrl = (prio | level) | (~intctrl_mask);
-
-	ECLIC_CTRL[irq].INTCTRL = intctrl;
-
-	union CLICINTATTR intattr = {.w = 0};
-
-	/* Set non-vectoring as default. */
-	intattr.b.shv = 0;
-	intattr.b.trg = (uint8_t)(flags & CLIC_INTATTR_TRIG_Msk);
-	ECLIC_CTRL[irq].INTATTR = intattr;
+	const struct device *dev = DEVICE_DT_INST_GET(0);
+	const struct clic_config *config = dev->config;
+	const struct clic_data *data = dev->data;
+
+	/*
+	 * Set the interrupt level and the interrupt priority.
+	 * Examples of mcliccfg settings:
+	 * CLICINTCTLBITS mnlbits clicintctl[i] interrupt levels
+	 *       0         2      ........      255
+	 *       1         2      l.......      127,255
+	 *       2         2      ll......      63,127,191,255
+	 *       3         3      lll.....      31,63,95,127,159,191,223,255
+	 *       4         1      lppp....      127,255
+	 * "." bits are non-existent bits for level encoding, assumed to be 1
+	 * "l" bits are available variable bits in level specification
+	 * "p" bits are available variable bits in priority specification
+	 */
+	const uint8_t max_level = BIT_MASK(data->nlbits);
+	const uint8_t max_prio = BIT_MASK(data->intctlbits - data->nlbits);
+	uint8_t intctrl = (MIN(pri, max_prio) << (8U - data->intctlbits)) |
+			  (MIN(pri, max_level) << (8U - data->nlbits)) |
+			  BIT_MASK(8U - data->intctlbits);
+
+	sys_write8(intctrl, config->base + CLIC_INTCTRL(irq));
+
+	/* Set the IRQ operates in machine mode, non-vectoring and the trigger type. */
+	union CLICINTATTR clicattr = {.b = {.mode = 0x3, .shv = 0x0, .trg = flags & BIT_MASK(3)}};
+
+	sys_write8(clicattr.w, config->base + CLIC_INTATTR(irq));
 }
 
 /**
  * @brief Set vector mode of interrupt
  */
 void riscv_clic_irq_vector_set(uint32_t irq)
 {
-	/* Set Selective Hardware Vectoring. */
-	union CLICINTATTR intattr = ECLIC_CTRL[irq].INTATTR;
+	const struct device *dev = DEVICE_DT_INST_GET(0);
+	const struct clic_config *config = dev->config;
+	union CLICINTATTR clicattr = {.w = sys_read8(config->base + CLIC_INTATTR(irq))};
 
-	intattr.b.shv = 1;
-	ECLIC_CTRL[irq].INTATTR = intattr;
+	/* Set Selective Hardware Vectoring. */
+	clicattr.b.shv = 1;
+	sys_write8(clicattr.w, config->base + CLIC_INTATTR(irq));
 }
 
 /**
  * @brief Set pending bit of an interrupt
  */
 void riscv_clic_irq_set_pending(uint32_t irq)
 {
-	ECLIC_CTRL[irq].INTIP.b.IP = 1;
+	const struct device *dev = DEVICE_DT_INST_GET(0);
+	const struct clic_config *config = dev->config;
+	union CLICINTIP clicintip = {.b = {.IP = 0x1}};
+
+	sys_write8(clicintip.w, config->base + CLIC_INTIP(irq));
 }
 
-static int nuclei_eclic_init(const struct device *dev)
+static int clic_init(const struct device *dev)
 {
-	ECLIC_MTH.w = 0;
-	ECLIC_CFG.w = 0;
-	ECLIC_CFG.b.nlbits = 0;
-	for (int i = 0; i < ECLIC_CTRL_SIZE; i++) {
-		ECLIC_CTRL[i] = (struct CLICCTRL) { 0 };
+	const struct clic_config *config = dev->config;
+	struct clic_data *data = dev->data;
+
+	if (IS_ENABLED(CONFIG_NUCLEI_ECLIC)) {
+		/* Configure the interrupt level threshold. */
+		union CLICMTH clicmth = {.b = {.mth = 0x0}};
+
+		sys_write32(clicmth.qw, config->base + CLIC_MTH);
+
+		/* Detect the number of bits for the clicintctl register. */
+		union CLICINFO clicinfo = {.qw = sys_read32(config->base + CLIC_INFO)};
+
+		data->intctlbits = clicinfo.b.intctlbits;
+
+		if (data->nlbits > data->intctlbits) {
+			data->nlbits = data->intctlbits;
+		}
+
+		/* Configure the number of bits assigned to interrupt levels. */
+		union CLICCFG cliccfg = {.qw = sys_read32(config->base + CLIC_CFG)};
+
+		cliccfg.w.nlbits = data->nlbits;
+		sys_write32(cliccfg.qw, config->base + CLIC_CFG);
+	} else {
+		/* Configure the interrupt level threshold by CSR mintthresh. */
+		csr_write(CSR_MINTTHRESH, 0x0);
 	}
 
-	nlbits = ECLIC_CFG.b.nlbits;
-	intctlbits = ECLIC_INFO.b.intctlbits;
-	max_prio = mask8(intctlbits - nlbits);
-	max_level = mask8(nlbits);
-	intctrl_mask = leftalign8(mask8(intctlbits), intctlbits);
+	/* Reset all interrupt control register */
+	for (int i = 0; i < CONFIG_NUM_IRQS; i++) {
+		sys_write32(0, config->base + CLIC_CTRL(i));
+	}
 
 	return 0;
 }
 
-DEVICE_DT_INST_DEFINE(0, nuclei_eclic_init, NULL, NULL, NULL,
-		      PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
+#define CLIC_INTC_DATA_INIT(n)                                                                     \
+	static struct clic_data clic_data_##n = {                                                  \
+		.nlbits = 0,                                                                       \
+		.intctlbits = 8,                                                                   \
+	};
+#define CLIC_INTC_CONFIG_INIT(n)                                                                   \
+	const static struct clic_config clic_config_##n = {                                        \
+		.base = DT_REG_ADDR(DT_DRV_INST(n)),                                               \
+	};
+#define CLIC_INTC_DEVICE_INIT(n)                                                                   \
+	CLIC_INTC_DATA_INIT(n)                                                                     \
+	CLIC_INTC_CONFIG_INIT(n)                                                                   \
+	DEVICE_DT_INST_DEFINE(n, &clic_init, NULL, &clic_data_##n, &clic_config_##n, PRE_KERNEL_1, \
+			      CONFIG_INTC_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(CLIC_INTC_DEVICE_INIT)