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drivers: crypto: Add STM32 HASH hardware driver
Add STM32 HASH driver with SHA-224/256 support for STM32U5 Signed-off-by: Bayrem Gharsellaoui <[email protected]>
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‎drivers/crypto/CMakeLists.txt

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@@ -4,6 +4,7 @@ zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_ATAES132A crypto_ataes132a.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_MBEDTLS_SHIM crypto_mtls_shim.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_STM32 crypto_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_STM32_HASH crypto_stm32_hash.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_SMARTBOND crypto_smartbond.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_NRF_ECB crypto_nrf_ecb.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_INTEL_SHA crypto_intel_sha.c)

‎drivers/crypto/Kconfig.stm32

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@@ -19,3 +19,21 @@ config CRYPTO_STM32_MAX_SESSION
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help
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This can be used to tweak the amount of sessions the driver
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can handle in parallel.
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config CRYPTO_STM32_HASH
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bool "STM32 Hash Accelerator driver"
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default y
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depends on DT_HAS_ST_STM32_HASH_ENABLED
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select USE_STM32_HAL_HASH
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select USE_STM32_HAL_HASH_EX
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help
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Enable support for the STM32 HASH hardware accelerator (SHA224/SHA256),
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using the STM32 HAL HASH driver.
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config CRYPTO_STM32_HASH_MAX_SESSIONS
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int "Maximum of sessions STM32 hash driver can handle"
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default 2
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depends on CRYPTO_STM32_HASH
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help
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This can be used to tweak the amount of sessions the driver
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can handle in parallel.

‎drivers/crypto/crypto_stm32_hash.c

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/*
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* Copyright (c) 2025 Bayrem Gharsellaoui
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/crypto/crypto.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/reset.h>
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#include <soc.h>
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#include "crypto_stm32_hash_priv.h"
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#define LOG_LEVEL CONFIG_CRYPTO_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(crypto_stm32_hash);
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#define DT_DRV_COMPAT st_stm32_hash
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static struct crypto_stm32_hash_session stm32_hash_sessions[CONFIG_CRYPTO_STM32_HASH_MAX_SESSIONS];
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static int crypto_stm32_hash_get_unused_session_index(const struct device *dev)
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{
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struct crypto_stm32_hash_data *data = CRYPTO_STM32_HASH_DATA(dev);
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k_sem_take(&data->session_sem, K_FOREVER);
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for (int i = 0; i < CONFIG_CRYPTO_STM32_HASH_MAX_SESSIONS; i++) {
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if (!stm32_hash_sessions[i].in_use) {
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stm32_hash_sessions[i].in_use = true;
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k_sem_give(&data->session_sem);
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return i;
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}
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}
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k_sem_give(&data->session_sem);
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return -1;
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}
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static int stm32_hash_handler(struct hash_ctx *ctx, struct hash_pkt *pkt, bool finish)
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{
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const struct device *dev = ctx->device;
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struct crypto_stm32_hash_data *data = CRYPTO_STM32_HASH_DATA(dev);
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struct crypto_stm32_hash_session *session = CRYPTO_STM32_HASH_SESSN(ctx);
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HAL_StatusTypeDef status;
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if (!pkt || !pkt->in_buf || !pkt->out_buf) {
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LOG_ERR("Invalid packet buffers");
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return -EINVAL;
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}
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if (!finish) {
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LOG_ERR("Multipart hashing not supported yet");
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return -ENOTSUP;
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}
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k_sem_take(&data->device_sem, K_FOREVER);
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switch (session->algo) {
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case CRYPTO_HASH_ALGO_SHA224:
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status = HAL_HASHEx_SHA224_Start(&data->hhash, pkt->in_buf, pkt->in_len,
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pkt->out_buf, HAL_MAX_DELAY);
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break;
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case CRYPTO_HASH_ALGO_SHA256:
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status = HAL_HASHEx_SHA256_Start(&data->hhash, pkt->in_buf, pkt->in_len,
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pkt->out_buf, HAL_MAX_DELAY);
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break;
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default:
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k_sem_give(&data->device_sem);
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LOG_ERR("Unsupported algorithm in handler: %d", session->algo);
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return -EINVAL;
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}
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k_sem_give(&data->device_sem);
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if (status != HAL_OK) {
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LOG_ERR("HAL HASH computation failed (status=%d)", status);
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return -EIO;
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}
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LOG_DBG("Hash computation successful");
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return 0;
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}
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static int stm32_hash_begin_session(const struct device *dev, struct hash_ctx *ctx,
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enum hash_algo algo)
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{
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int ctx_idx;
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struct crypto_stm32_hash_session *session;
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switch (algo) {
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case CRYPTO_HASH_ALGO_SHA224:
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case CRYPTO_HASH_ALGO_SHA256:
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break;
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default:
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LOG_ERR("Unsupported hash algorithm: %d", algo);
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return -EINVAL;
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}
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ctx_idx = crypto_stm32_hash_get_unused_session_index(dev);
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if (ctx_idx < 0) {
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LOG_ERR("No free session for now");
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return -ENOSPC;
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}
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session = &stm32_hash_sessions[ctx_idx];
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memset(&session->config, 0, sizeof(session->config));
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memset(session->digest, 0, sizeof(session->digest));
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session->in_use = true;
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session->algo = algo;
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ctx->drv_sessn_state = session;
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ctx->hash_hndlr = stm32_hash_handler;
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ctx->started = false;
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LOG_DBG("begin_session (algo=%d)", algo);
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return 0;
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}
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static int stm32_hash_free_session(const struct device *dev, struct hash_ctx *ctx)
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{
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struct crypto_stm32_hash_session *session = CRYPTO_STM32_HASH_SESSN(ctx);
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if (!session) {
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LOG_ERR("Tried to free a NULL session");
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return -EINVAL;
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}
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memset(session, 0, sizeof(*session));
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LOG_DBG("Session freed");
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return 0;
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}
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static int stm32_hash_query_caps(const struct device *dev)
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{
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return (CAP_SYNC_OPS | CAP_SEPARATE_IO_BUFS);
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}
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static int crypto_stm32_hash_init(const struct device *dev)
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{
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const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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const struct crypto_stm32_hash_config *cfg = CRYPTO_STM32_HASH_CFG(dev);
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struct crypto_stm32_hash_data *data = CRYPTO_STM32_HASH_DATA(dev);
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if (!device_is_ready(clk)) {
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LOG_ERR("Clock control device not ready");
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return -ENODEV;
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}
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if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken) != 0) {
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LOG_ERR("Clock op failed\n");
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return -EIO;
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}
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k_sem_init(&data->device_sem, 1, 1);
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k_sem_init(&data->session_sem, 1, 1);
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data->hhash.Init.DataType = HASH_DATATYPE_8B;
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if (HAL_HASH_Init(&data->hhash) != HAL_OK) {
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LOG_ERR("Peripheral init error");
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return -EIO;
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}
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return 0;
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}
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static DEVICE_API(crypto, stm32_hash_funcs) = {
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.hash_begin_session = stm32_hash_begin_session,
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.hash_free_session = stm32_hash_free_session,
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.query_hw_caps = stm32_hash_query_caps,
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};
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static struct crypto_stm32_hash_data crypto_stm32_hash_dev_data = {0};
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static const struct crypto_stm32_hash_config crypto_stm32_hash_dev_config = {
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.reset = RESET_DT_SPEC_INST_GET(0),
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.pclken = {.enr = DT_INST_CLOCKS_CELL(0, bits), .bus = DT_INST_CLOCKS_CELL(0, bus)}};
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DEVICE_DT_INST_DEFINE(0, crypto_stm32_hash_init, NULL, &crypto_stm32_hash_dev_data,
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&crypto_stm32_hash_dev_config, POST_KERNEL, CONFIG_CRYPTO_INIT_PRIORITY,
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&stm32_hash_funcs);

‎drivers/crypto/crypto_stm32_hash_priv.h

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/*
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* Copyright (c) 2025 Bayrem Gharsellaoui
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_CRYPTO_CRYPTO_STM32_HASH_PRIV_H_
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#define ZEPHYR_DRIVERS_CRYPTO_CRYPTO_STM32_HASH_PRIV_H_
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#define hash_config_t HASH_InitTypeDef
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/* Max digest length: SHA256 = 32 bytes */
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#define STM32_HASH_MAX_DIGEST_SIZE (32)
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struct crypto_stm32_hash_config {
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const struct reset_dt_spec reset;
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struct stm32_pclken pclken;
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};
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struct crypto_stm32_hash_data {
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HASH_HandleTypeDef hhash;
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struct k_sem device_sem;
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struct k_sem session_sem;
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};
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struct crypto_stm32_hash_session {
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hash_config_t config;
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uint8_t digest[STM32_HASH_MAX_DIGEST_SIZE];
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bool in_use;
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enum hash_algo algo;
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};
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#define CRYPTO_STM32_HASH_CFG(dev) ((const struct crypto_stm32_hash_config *const)(dev)->config)
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#define CRYPTO_STM32_HASH_DATA(dev) ((struct crypto_stm32_hash_data *const)(dev)->data)
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#define CRYPTO_STM32_HASH_SESSN(ctx) \
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((struct crypto_stm32_hash_session *const)(ctx)->drv_sessn_state)
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#endif /* ZEPHYR_DRIVERS_CRYPTO_CRYPTO_STM32_HASH_PRIV_H_ */

‎dts/bindings/crypto/st,stm32-hash.yaml

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# Copyright (c) 2025 Bayrem Gharsellaoui
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# SPDX-License-Identifier: Apache-2.0
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title: STM32 HASH Processor
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description: |
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STM32 hardware hash accelerator supporting SHA-224 and SHA-256
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hashing algorithms.
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compatible: "st,stm32-hash"
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include: [base.yaml, reset-device.yaml]
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properties:
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reg:
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required: true
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clocks:
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required: true
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resets:
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required: true

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