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gbernatxintel
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soc: intel: Fix problems with the formatter
No functional changes were made in this update. Only code formatting issues were corrected. This commit is necessary to preserve Git history continuity for future changes involving the switch from ace30_ptl to ace30. Signed-off-by: Grzegorz Bernat <[email protected]>
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6 files changed

+167
-172
lines changed

6 files changed

+167
-172
lines changed

‎soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_boot.h‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
#ifndef ZEPHYR_SOC_INTEL_ADSP_BOOT_H_
77
#define ZEPHYR_SOC_INTEL_ADSP_BOOT_H_
88

9-
#define DSPCS_REG 0x178d00
9+
#define DSPCS_REG 0x178d00
1010

1111
struct dspcs {
1212
/*
@@ -43,21 +43,21 @@ struct dspcs {
4343
} bootctl[5];
4444
};
4545

46-
#define DSPCS_CTL_SPA BIT(0)
47-
#define DSPCS_CTL_CPA BIT(8)
46+
#define DSPCS_CTL_SPA BIT(0)
47+
#define DSPCS_CTL_CPA BIT(8)
4848

49-
#define DSPBR_BCTL_BYPROM BIT(0)
50-
#define DSPBR_BCTL_WAITIPCG BIT(16)
51-
#define DSPBR_BCTL_WAITIPPG BIT(17)
49+
#define DSPBR_BCTL_BYPROM BIT(0)
50+
#define DSPBR_BCTL_WAITIPCG BIT(16)
51+
#define DSPBR_BCTL_WAITIPPG BIT(17)
5252

53-
#define DSPBR_BATTR_LPSCTL_RESTORE_BOOT BIT(12)
54-
#define DSPBR_BATTR_LPSCTL_HP_CLOCK_BOOT BIT(13)
55-
#define DSPBR_BATTR_LPSCTL_LP_CLOCK_BOOT BIT(14)
56-
#define DSPBR_BATTR_LPSCTL_L1_MIN_WAY BIT(15)
57-
#define DSPBR_BATTR_LPSCTL_BATTR_SLAVE_CORE BIT(16)
53+
#define DSPBR_BATTR_LPSCTL_RESTORE_BOOT BIT(12)
54+
#define DSPBR_BATTR_LPSCTL_HP_CLOCK_BOOT BIT(13)
55+
#define DSPBR_BATTR_LPSCTL_LP_CLOCK_BOOT BIT(14)
56+
#define DSPBR_BATTR_LPSCTL_L1_MIN_WAY BIT(15)
57+
#define DSPBR_BATTR_LPSCTL_BATTR_SLAVE_CORE BIT(16)
5858

59-
#define DSPBR_WDT_RESUME BIT(8)
60-
#define DSPBR_WDT_RESTART_COMMAND 0x76
59+
#define DSPBR_WDT_RESUME BIT(8)
60+
#define DSPBR_WDT_RESTART_COMMAND 0x76
6161

6262
#define DSPCS (*(volatile struct dspcs *)DSPCS_REG)
6363

‎soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_interrupt.h‎

Lines changed: 29 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -7,35 +7,35 @@
77
#define ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_
88

99
/* Low priority interrupt indices */
10-
#define ACE_INTL_HIPC 0
11-
#define ACE_INTL_SBIPC 1
12-
#define ACE_INTL_ML 2
13-
#define ACE_INTL_IDCA 3
14-
#define ACE_INTL_LPVML 4
15-
#define ACE_INTL_SHA 5
16-
#define ACE_INTL_L1L2M 6
17-
#define ACE_INTL_I2S 7
18-
#define ACE_INTL_DMIC 8
19-
#define ACE_INTL_SNDW 9
20-
#define ACE_INTL_TTS 10
21-
#define ACE_INTL_WDT 11
10+
#define ACE_INTL_HIPC 0
11+
#define ACE_INTL_SBIPC 1
12+
#define ACE_INTL_ML 2
13+
#define ACE_INTL_IDCA 3
14+
#define ACE_INTL_LPVML 4
15+
#define ACE_INTL_SHA 5
16+
#define ACE_INTL_L1L2M 6
17+
#define ACE_INTL_I2S 7
18+
#define ACE_INTL_DMIC 8
19+
#define ACE_INTL_SNDW 9
20+
#define ACE_INTL_TTS 10
21+
#define ACE_INTL_WDT 11
2222
#define ACE_INTL_HDAHIDMA 12
2323
#define ACE_INTL_HDAHODMA 13
2424
#define ACE_INTL_HDALIDMA 14
2525
#define ACE_INTL_HDALODMA 15
26-
#define ACE_INTL_I3C 16
27-
#define ACE_INTL_GPDMA 17
28-
#define ACE_INTL_PWM 18
29-
#define ACE_INTL_I2C 19
30-
#define ACE_INTL_SPI 20
31-
#define ACE_INTL_UART 21
32-
#define ACE_INTL_GPIO 22
33-
#define ACE_INTL_UAOL 23
34-
#define ACE_INTL_IDCB 24
35-
#define ACE_INTL_DCW 25
36-
#define ACE_INTL_DTF 26
37-
#define ACE_INTL_FLV 27
38-
#define ACE_INTL_DPDMA 28
26+
#define ACE_INTL_I3C 16
27+
#define ACE_INTL_GPDMA 17
28+
#define ACE_INTL_PWM 18
29+
#define ACE_INTL_I2C 19
30+
#define ACE_INTL_SPI 20
31+
#define ACE_INTL_UART 21
32+
#define ACE_INTL_GPIO 22
33+
#define ACE_INTL_UAOL 23
34+
#define ACE_INTL_IDCB 24
35+
#define ACE_INTL_DCW 25
36+
#define ACE_INTL_DTF 26
37+
#define ACE_INTL_FLV 27
38+
#define ACE_INTL_DPDMA 28
3939

4040
/* Device interrupt control for the low priority interrupts. It
4141
* provides per-core masking and status checking: ACE_DINT is an array
@@ -71,14 +71,14 @@ struct ace_dint {
7171
*/
7272
#define DXHIPCIE_REG 0x91040
7373

74-
#define ACE_DINT ((volatile struct ace_dint *)DXHIPCIE_REG)
74+
#define ACE_DINT ((volatile struct ace_dint *)DXHIPCIE_REG)
7575
#define XTENSA_IRQ_NUM_MASK 0xff
7676
#define XTENSA_IRQ_NUM_SHIFT 0
7777

78-
#define XTENSA_IRQ_NUMBER(_irq) ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
78+
#define XTENSA_IRQ_NUMBER(_irq) ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
7979
/* Convert between IRQ_CONNECT() numbers and ACE_INTL_* interrupts */
80-
#define ACE_IRQ_NUM_SHIFT 8
81-
#define ACE_IRQ_NUM_MASK 0xFFU
80+
#define ACE_IRQ_NUM_SHIFT 8
81+
#define ACE_IRQ_NUM_MASK 0xFFU
8282
#define ACE_IRQ_FROM_ZEPHYR(_irq) (((_irq >> ACE_IRQ_NUM_SHIFT) & ACE_IRQ_NUM_MASK) - 1)
8383

8484
#define ACE_INTC_IRQ DT_IRQN(DT_NODELABEL(ace_intc))

‎soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_ipc_regs.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,8 @@ struct intel_adsp_ipc {
4444
* This clears BUSY on the other side of the connection in IDR register.
4545
*/
4646
#define INTEL_ADSP_IPC_ACE1X_TDA_DONE 0
47-
#define INTEL_ADSP_IPC_BUSY BIT(31)
48-
#define INTEL_ADSP_IPC_DONE BIT(31)
47+
#define INTEL_ADSP_IPC_BUSY BIT(31)
48+
#define INTEL_ADSP_IPC_DONE BIT(31)
4949

5050
#define INTEL_ADSP_IPC_CTL_TBIE BIT(0)
5151
#define INTEL_ADSP_IPC_CTL_IDIE BIT(1)

‎soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_power.h‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -16,45 +16,45 @@
1616

1717
/* Power Control register - controls the power domain operations. */
1818
struct ace_pwrctl {
19-
uint16_t rsvd4 : 5;
20-
uint16_t wphstpg : 1;
21-
uint16_t wphubhppg : 1;
22-
uint16_t wpdspulppg : 1;
23-
uint16_t wpioxpg : 2;
24-
uint16_t rsvd11 : 2;
25-
uint16_t wpmlpg : 1;
26-
uint16_t rsvd14 : 2;
27-
uint16_t phubulppg : 1;
19+
uint16_t rsvd4: 5;
20+
uint16_t wphstpg: 1;
21+
uint16_t wphubhppg: 1;
22+
uint16_t wpdspulppg: 1;
23+
uint16_t wpioxpg: 2;
24+
uint16_t rsvd11: 2;
25+
uint16_t wpmlpg: 1;
26+
uint16_t rsvd14: 2;
27+
uint16_t phubulppg: 1;
2828
};
2929

3030
struct ace_pwrctl2 {
31-
uint16_t wpdsphpxpg : 5;
32-
uint16_t rsvd15 : 11;
31+
uint16_t wpdsphpxpg: 5;
32+
uint16_t rsvd15: 11;
3333
};
3434

35-
#define ACE_PWRCTL ((volatile struct ace_pwrctl *) &ACE_DfPMCCU.dfpwrctl)
36-
#define ACE_PWRCTL2 ((volatile struct ace_pwrctl2 *) &ACE_DfPMCCU.dfpwrctl2)
35+
#define ACE_PWRCTL ((volatile struct ace_pwrctl *)&ACE_DfPMCCU.dfpwrctl)
36+
#define ACE_PWRCTL2 ((volatile struct ace_pwrctl2 *)&ACE_DfPMCCU.dfpwrctl2)
3737

3838
/* Power Status register - reports the power domain status. */
3939
struct ace_pwrsts {
40-
uint16_t rsvd4 : 5;
41-
uint16_t hstpgs : 1;
42-
uint16_t hubhppgs : 1;
43-
uint16_t dspulppgs : 1;
44-
uint16_t ioxpgs : 2;
45-
uint16_t rsvd11 : 2;
46-
uint16_t mlpgs : 1;
47-
uint16_t rsvd14 : 2;
48-
uint16_t hubulppgs : 1;
40+
uint16_t rsvd4: 5;
41+
uint16_t hstpgs: 1;
42+
uint16_t hubhppgs: 1;
43+
uint16_t dspulppgs: 1;
44+
uint16_t ioxpgs: 2;
45+
uint16_t rsvd11: 2;
46+
uint16_t mlpgs: 1;
47+
uint16_t rsvd14: 2;
48+
uint16_t hubulppgs: 1;
4949
};
5050

5151
struct ace_pwrsts2 {
52-
uint16_t dsphpxpgs : 5;
53-
uint16_t rsvd15 : 11;
52+
uint16_t dsphpxpgs: 5;
53+
uint16_t rsvd15: 11;
5454
};
5555

56-
#define ACE_PWRSTS ((volatile struct ace_pwrsts *) &ACE_DfPMCCU.dfpwrsts)
57-
#define ACE_PWRSTS2 ((volatile struct ace_pwrsts2 *) &ACE_DfPMCCU.dfpwrsts2)
56+
#define ACE_PWRSTS ((volatile struct ace_pwrsts *)&ACE_DfPMCCU.dfpwrsts)
57+
#define ACE_PWRSTS2 ((volatile struct ace_pwrsts2 *)&ACE_DfPMCCU.dfpwrsts2)
5858

5959
/**
6060
* @brief Power up a specific CPU.

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