|
95 | 95 | };
|
96 | 96 | };
|
97 | 97 |
|
| 98 | + icu: icu@81048000 { |
| 99 | + reg = <0x81048000 0x1000>; |
| 100 | + interrupt-parent = <&gic>; |
| 101 | + #address-cells = <1>; |
| 102 | + #size-cells = <0>; |
| 103 | + |
| 104 | + irq0: irq0@0 { |
| 105 | + compatible = "renesas,rz-ext-irq"; |
| 106 | + reg = <0x0>; |
| 107 | + interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 108 | + interrupt-controller; |
| 109 | + #interrupt-cells = <2>; |
| 110 | + status = "disabled"; |
| 111 | + }; |
| 112 | + |
| 113 | + irq1: irq@1 { |
| 114 | + compatible = "renesas,rz-ext-irq"; |
| 115 | + reg = <0x1>; |
| 116 | + interrupts = <GIC_SPI 7 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 117 | + interrupt-controller; |
| 118 | + #interrupt-cells = <2>; |
| 119 | + status = "disabled"; |
| 120 | + }; |
| 121 | + |
| 122 | + irq2: irq@2 { |
| 123 | + compatible = "renesas,rz-ext-irq"; |
| 124 | + reg = <0x2>; |
| 125 | + interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 126 | + interrupt-controller; |
| 127 | + #interrupt-cells = <2>; |
| 128 | + status = "disabled"; |
| 129 | + }; |
| 130 | + |
| 131 | + irq3: irq@3 { |
| 132 | + compatible = "renesas,rz-ext-irq"; |
| 133 | + reg = <0x3>; |
| 134 | + interrupts = <GIC_SPI 9 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 135 | + interrupt-controller; |
| 136 | + #interrupt-cells = <2>; |
| 137 | + status = "disabled"; |
| 138 | + }; |
| 139 | + |
| 140 | + irq4: irq@4 { |
| 141 | + compatible = "renesas,rz-ext-irq"; |
| 142 | + reg = <0x4>; |
| 143 | + interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 144 | + interrupt-controller; |
| 145 | + #interrupt-cells = <2>; |
| 146 | + status = "disabled"; |
| 147 | + }; |
| 148 | + |
| 149 | + irq5: irq@5 { |
| 150 | + compatible = "renesas,rz-ext-irq"; |
| 151 | + reg = <0x5>; |
| 152 | + interrupts = <GIC_SPI 11 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 153 | + interrupt-controller; |
| 154 | + #interrupt-cells = <2>; |
| 155 | + status = "disabled"; |
| 156 | + }; |
| 157 | + |
| 158 | + irq6: irq@6 { |
| 159 | + compatible = "renesas,rz-ext-irq"; |
| 160 | + reg = <0x6>; |
| 161 | + interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 162 | + interrupt-controller; |
| 163 | + #interrupt-cells = <2>; |
| 164 | + status = "disabled"; |
| 165 | + }; |
| 166 | + |
| 167 | + irq7: irq@7 { |
| 168 | + compatible = "renesas,rz-ext-irq"; |
| 169 | + reg = <0x7>; |
| 170 | + interrupts = <GIC_SPI 13 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 171 | + interrupt-controller; |
| 172 | + #interrupt-cells = <2>; |
| 173 | + status = "disabled"; |
| 174 | + }; |
| 175 | + |
| 176 | + irq8: irq@8 { |
| 177 | + compatible = "renesas,rz-ext-irq"; |
| 178 | + reg = <0x8>; |
| 179 | + interrupts = <GIC_SPI 14 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 180 | + interrupt-controller; |
| 181 | + #interrupt-cells = <2>; |
| 182 | + status = "disabled"; |
| 183 | + }; |
| 184 | + |
| 185 | + irq9: irq@9 { |
| 186 | + compatible = "renesas,rz-ext-irq"; |
| 187 | + reg = <0x9>; |
| 188 | + interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 189 | + interrupt-controller; |
| 190 | + #interrupt-cells = <2>; |
| 191 | + status = "disabled"; |
| 192 | + }; |
| 193 | + |
| 194 | + irq10: irq@a { |
| 195 | + compatible = "renesas,rz-ext-irq"; |
| 196 | + reg = <0xa>; |
| 197 | + interrupts = <GIC_SPI 16 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 198 | + interrupt-controller; |
| 199 | + #interrupt-cells = <2>; |
| 200 | + status = "disabled"; |
| 201 | + }; |
| 202 | + |
| 203 | + irq11: irq@b { |
| 204 | + compatible = "renesas,rz-ext-irq"; |
| 205 | + reg = <0xb>; |
| 206 | + interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 207 | + interrupt-controller; |
| 208 | + #interrupt-cells = <2>; |
| 209 | + status = "disabled"; |
| 210 | + }; |
| 211 | + |
| 212 | + irq12: irq@c { |
| 213 | + compatible = "renesas,rz-ext-irq"; |
| 214 | + reg = <0xc>; |
| 215 | + interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 216 | + interrupt-controller; |
| 217 | + #interrupt-cells = <2>; |
| 218 | + status = "disabled"; |
| 219 | + }; |
| 220 | + |
| 221 | + irq13: irq@d { |
| 222 | + compatible = "renesas,rz-ext-irq"; |
| 223 | + reg = <0xd>; |
| 224 | + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 225 | + interrupt-controller; |
| 226 | + #interrupt-cells = <2>; |
| 227 | + status = "disabled"; |
| 228 | + }; |
| 229 | + |
| 230 | + irq14: irq@e { |
| 231 | + compatible = "renesas,rz-ext-irq"; |
| 232 | + reg = <0xe>; |
| 233 | + interrupts = <GIC_SPI 394 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 234 | + interrupt-controller; |
| 235 | + #interrupt-cells = <2>; |
| 236 | + status = "disabled"; |
| 237 | + }; |
| 238 | + |
| 239 | + irq15: irq@f { |
| 240 | + compatible = "renesas,rz-ext-irq"; |
| 241 | + reg = <0xf>; |
| 242 | + interrupts = <GIC_SPI 395 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>; |
| 243 | + interrupt-controller; |
| 244 | + #interrupt-cells = <2>; |
| 245 | + status = "disabled"; |
| 246 | + }; |
| 247 | + }; |
| 248 | + |
98 | 249 | pinctrl: pinctrl@800a0000 {
|
99 | 250 | compatible = "renesas,rzt-pinctrl";
|
100 | 251 | reg = <0x800a0000 0x1000 0x81030c00 0x1000>;
|
|
0 commit comments