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| 1 | +/* |
| 2 | + * Copyright (c) 2024 Analog Devices, Inc. |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX78002_DMA_H_ |
| 8 | +#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX78002_DMA_H_ |
| 9 | + |
| 10 | +#define MAX78_DMA_SLOT_MEMTOMEM 0x00U |
| 11 | +#define MAX78_DMA_SLOT_SPI1_RX 0x01U |
| 12 | +#define MAX78_DMA_SLOT_UART0_RX 0x04U |
| 13 | +#define MAX78_DMA_SLOT_UART1_RX 0x05U |
| 14 | +#define MAX78_DMA_SLOT_I2C0_RX 0x07U |
| 15 | +#define MAX78_DMA_SLOT_I2C1_RX 0x08U |
| 16 | +#define MAX78_DMA_SLOT_ADC 0x09U |
| 17 | +#define MAX78_DMA_SLOT_I2C2_RX 0x0AU |
| 18 | +#define MAX78_DMA_SLOT_UART2_RX 0x0EU |
| 19 | +#define MAX78_DMA_SLOT_SPI0_RX 0x0FU |
| 20 | +#define MAX78_DMA_SLOT_AES_RX 0x10U |
| 21 | +#define MAX78_DMA_SLOT_I2S_RX 0x1EU |
| 22 | +#define MAX78_DMA_SLOT_SPI1_TX 0x21U |
| 23 | +#define MAX78_DMA_SLOT_UART0_TX 0x24U |
| 24 | +#define MAX78_DMA_SLOT_UART1_TX 0x25U |
| 25 | +#define MAX78_DMA_SLOT_I2C0_TX 0x27U |
| 26 | +#define MAX78_DMA_SLOT_I2C1_TX 0x28U |
| 27 | +#define MAX78_DMA_SLOT_I2C2_TX 0x2AU |
| 28 | +#define MAX78_DMA_SLOT_CRC 0x2CU |
| 29 | +#define MAX78_DMA_SLOT_UART2_TX 0x2EU |
| 30 | +#define MAX78_DMA_SLOT_SPI0_TX 0x2FU |
| 31 | +#define MAX78_DMA_SLOT_AES_TX 0x30U |
| 32 | +#define MAX78_DMA_SLOT_I2S_TX 0x3EU |
| 33 | + |
| 34 | +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX78002_DMA_H_ */ |
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