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Raffael Rostagno
committed
drivers: clock_control: esp32h2: Add support
Add clocl control support for ESP32-H2. Signed-off-by: Raffael Rostagno <[email protected]>
1 parent 5437eed commit 9fb57dc

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3 files changed

+161
-19
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3 files changed

+161
-19
lines changed

‎drivers/clock_control/clock_control_esp32.c

Lines changed: 69 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,8 @@
99

1010
#define CPU_RESET_REASON RTC_SW_CPU_RESET
1111

12+
#include <stddef.h>
13+
1214
#if defined(CONFIG_SOC_SERIES_ESP32)
1315
#define DT_CPU_COMPAT espressif_xtensa_lx6
1416
#undef CPU_RESET_REASON
@@ -49,6 +51,18 @@
4951
#include <esp_private/esp_pmu.h>
5052
#include <esp_private/esp_modem_clock.h>
5153
#include <ocode_init.h>
54+
#elif defined(CONFIG_SOC_SERIES_ESP32H2)
55+
#define DT_CPU_COMPAT espressif_riscv
56+
#include <zephyr/dt-bindings/clock/esp32h2_clock.h>
57+
#include <soc/lpperi_reg.h>
58+
#include <soc/lp_clkrst_reg.h>
59+
#include <regi2c_ctrl.h>
60+
#include <esp32h2/rom/rtc.h>
61+
#include <soc/dport_access.h>
62+
#include <hal/clk_tree_ll.h>
63+
#include <hal/usb_serial_jtag_ll.h>
64+
#include <esp_private/esp_pmu.h>
65+
#include <esp_sleep.h>
5266
#endif
5367

5468
#include <zephyr/drivers/clock_control.h>
@@ -85,10 +99,13 @@ static bool reset_reason_is_cpu_reset(void)
8599
return false;
86100
}
87101

88-
#if defined(CONFIG_SOC_SERIES_ESP32C6)
102+
#if defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2)
89103
static void esp32_clock_perip_init(void)
90104
{
91105
soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get();
106+
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
107+
108+
#if defined(CONFIG_SOC_SERIES_ESP32C6)
92109
modem_clock_lpclk_src_t modem_lpclk_src =
93110
(modem_clock_lpclk_src_t)((rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW)
94111
? MODEM_CLOCK_LPCLK_SRC_RC_SLOW
@@ -101,19 +118,36 @@ static void esp32_clock_perip_init(void)
101118
: MODEM_CLOCK_LPCLK_SRC_RC_SLOW);
102119

103120
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
104-
105-
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
121+
#elif defined(CONFIG_SOC_SERIES_ESP32H2)
122+
esp_sleep_pd_domain_t pu_domain =
123+
(esp_sleep_pd_domain_t)((rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K)
124+
? ESP_PD_DOMAIN_XTAL32K
125+
: (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K)
126+
? ESP_PD_DOMAIN_RC32K
127+
: ESP_PD_DOMAIN_MAX);
128+
esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON);
129+
#endif
106130

107131
if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) &&
108132
(rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT)) {
109133

134+
#if CONFIG_ESP_CONSOLE_UART_NUM != 0
135+
periph_ll_disable_clk_set_rst(PERIPH_UART0_MODULE);
136+
#endif
137+
#if CONFIG_ESP_CONSOLE_UART_NUM != 1
110138
periph_ll_disable_clk_set_rst(PERIPH_UART1_MODULE);
139+
#endif
111140
periph_ll_disable_clk_set_rst(PERIPH_I2C0_MODULE);
141+
#if defined(CONFIG_SOC_SERIES_ESP32H2)
142+
periph_ll_disable_clk_set_rst(PERIPH_I2C1_MODULE);
143+
#endif
112144
periph_ll_disable_clk_set_rst(PERIPH_RMT_MODULE);
113145
periph_ll_disable_clk_set_rst(PERIPH_LEDC_MODULE);
114146
periph_ll_disable_clk_set_rst(PERIPH_TIMG1_MODULE);
115147
periph_ll_disable_clk_set_rst(PERIPH_TWAI0_MODULE);
148+
#if defined(CONFIG_SOC_SERIES_ESP32C6)
116149
periph_ll_disable_clk_set_rst(PERIPH_TWAI1_MODULE);
150+
#endif
117151
periph_ll_disable_clk_set_rst(PERIPH_I2S1_MODULE);
118152
periph_ll_disable_clk_set_rst(PERIPH_PCNT_MODULE);
119153
periph_ll_disable_clk_set_rst(PERIPH_ETM_MODULE);
@@ -124,17 +158,24 @@ static void esp32_clock_perip_init(void)
124158
periph_ll_disable_clk_set_rst(PERIPH_TEMPSENSOR_MODULE);
125159
periph_ll_disable_clk_set_rst(PERIPH_UHCI0_MODULE);
126160
periph_ll_disable_clk_set_rst(PERIPH_SARADC_MODULE);
161+
#if defined(CONFIG_SOC_SERIES_ESP32C6)
127162
periph_ll_disable_clk_set_rst(PERIPH_SDIO_SLAVE_MODULE);
163+
#endif
128164
periph_ll_disable_clk_set_rst(PERIPH_RSA_MODULE);
129165
periph_ll_disable_clk_set_rst(PERIPH_AES_MODULE);
130166
periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
131167
periph_ll_disable_clk_set_rst(PERIPH_ECC_MODULE);
132168
periph_ll_disable_clk_set_rst(PERIPH_HMAC_MODULE);
133169
periph_ll_disable_clk_set_rst(PERIPH_DS_MODULE);
170+
#if defined(CONFIG_SOC_SERIES_ESP32H2)
171+
periph_ll_disable_clk_set_rst(PERIPH_ECDSA_MODULE);
172+
#endif
134173

135174
REG_CLR_BIT(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
136175
REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN);
176+
#if defined(CONFIG_SOC_SERIES_ESP32C6)
137177
REG_CLR_BIT(PCR_RETENTION_CONF_REG, PCR_RETENTION_CLK_EN);
178+
#endif
138179
REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN);
139180
REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
140181
REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
@@ -150,8 +191,9 @@ static void esp32_clock_perip_init(void)
150191
(rst_reason == RESET_REASON_SYS_RTC_WDT) ||
151192
(rst_reason == RESET_REASON_SYS_SUPER_WDT)) {
152193

194+
#if defined(CONFIG_SOC_SERIES_ESP32C6)
153195
periph_ll_disable_clk_set_rst(PERIPH_LP_I2C0_MODULE);
154-
196+
#endif
155197
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_RNG_CK_EN);
156198
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_UART_CK_EN);
157199
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN);
@@ -544,7 +586,7 @@ static int clock_control_esp32_get_rate(const struct device *dev, clock_control_
544586

545587
static int esp32_select_rtc_slow_clk(uint8_t slow_clk)
546588
{
547-
#if !defined(CONFIG_SOC_SERIES_ESP32C6)
589+
#if !defined(CONFIG_SOC_SERIES_ESP32C6) && !defined(CONFIG_SOC_SERIES_ESP32H2)
548590
soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
549591
#else
550592
soc_rtc_slow_clk_src_t rtc_slow_clk_src = slow_clk;
@@ -600,7 +642,7 @@ static int esp32_select_rtc_slow_clk(uint8_t slow_clk)
600642
return -ENODEV;
601643
}
602644
}
603-
#if defined(CONFIG_SOC_SERIES_ESP32C6)
645+
#if defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2)
604646
} else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) {
605647
rtc_clk_rc32k_enable(true);
606648
}
@@ -642,11 +684,21 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf
642684
#if defined(CONFIG_SOC_SERIES_ESP32C6)
643685
rtc_clk_modem_clock_domain_active_state_icg_map_preinit();
644686

645-
REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, rtc_clk_cfg.clk_8m_dfreq);
646687
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap);
647-
REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, rtc_clk_cfg.rc32k_dfreq);
648688
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1);
649689
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
690+
#elif defined(CONFIG_SOC_SERIES_ESP32H2)
691+
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_OC_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap);
692+
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_RTC_DREG, 0);
693+
REGI2C_WRITE_MASK(I2C_PMU, I2C_PMU_EN_I2C_DIG_DREG, 0);
694+
#else
695+
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap);
696+
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, rtc_clk_cfg.clk_8m_dfreq);
697+
#endif
698+
699+
#if defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2)
700+
REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, rtc_clk_cfg.clk_8m_dfreq);
701+
REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, rtc_clk_cfg.rc32k_dfreq);
650702

651703
uint32_t hp_cali_dbias = get_act_hp_dbias();
652704
uint32_t lp_cali_dbias = get_act_lp_dbias();
@@ -657,15 +709,11 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf
657709
hp_cali_dbias, PMU_HP_MODEM_HP_REGULATOR_DBIAS_S);
658710
SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS,
659711
lp_cali_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S);
660-
661-
#else
662-
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, rtc_clk_cfg.slow_clk_dcap);
663-
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, rtc_clk_cfg.clk_8m_dfreq);
664712
#endif
665713

666714
#if defined(CONFIG_SOC_SERIES_ESP32)
667715
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, rtc_clk_cfg.clk_8m_div - 1);
668-
#elif defined(CONFIG_SOC_SERIES_ESP32C6)
716+
#elif defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32H2)
669717
clk_ll_rc_fast_tick_conf();
670718

671719
esp_rom_uart_tx_wait_idle(0);
@@ -678,7 +726,7 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf
678726
rtc_clk_8m_divider_set(rtc_clk_cfg.clk_8m_clk_div);
679727
#endif
680728

681-
#if !defined(CONFIG_SOC_SERIES_ESP32C6)
729+
#if !defined(CONFIG_SOC_SERIES_ESP32C6) && !defined(CONFIG_SOC_SERIES_ESP32H2)
682730
/* Reset (disable) i2c internal bus for all regi2c registers */
683731
regi2c_ctrl_ll_i2c_reset();
684732
/* Enable the internal bus used to configure BBPLL */
@@ -699,7 +747,7 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf
699747
* to make it run at 80MHz after the switch. PLL = 480MHz, so divider is 6.
700748
*/
701749
clk_ll_mspi_fast_set_hs_divider(6);
702-
#else
750+
#elif !defined(CONFIG_SOC_SERIES_ESP32H2)
703751
rtc_clk_apb_freq_update(rtc_clk_cfg.xtal_freq * MHZ(1));
704752
#endif
705753

@@ -719,7 +767,8 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf
719767
old_config.freq_mhz);
720768

721769
#if defined(CONFIG_ESP_CONSOLE_UART)
722-
#if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C6)
770+
#if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C6) && \
771+
!defined(CONFIG_SOC_SERIES_ESP32H2)
723772
#if defined(CONFIG_MCUBOOT) && defined(ESP_ROM_UART_CLK_IS_XTAL)
724773
uint32_t uart_clock_src_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ(1);
725774
#else
@@ -775,7 +824,9 @@ static int clock_control_esp32_init(const struct device *dev)
775824
if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
776825
esp_ocode_calib_init();
777826
}
778-
#else /* CONFIG_SOC_SERIES_ESP32C6 */
827+
#elif defined(CONFIG_SOC_SERIES_ESP32H2)
828+
pmu_init();
829+
#else /* CONFIG_SOC_SERIES_ESP32C6 || CONFIG_SOC_SERIES_ESP32H2 */
779830
rtc_config_t rtc_cfg = RTC_CONFIG_DEFAULT();
780831

781832
#if !defined(CONFIG_SOC_SERIES_ESP32)
@@ -788,7 +839,7 @@ static int clock_control_esp32_init(const struct device *dev)
788839
}
789840
#endif /* !CONFIG_SOC_SERIES_ESP32 */
790841
rtc_init(rtc_cfg);
791-
#endif /* CONFIG_SOC_SERIES_ESP32C6 */
842+
#endif /* CONFIG_SOC_SERIES_ESP32C6 || CONFIG_SOC_SERIES_ESP32H2 */
792843

793844
ret = esp32_cpu_clock_configure(&cfg->cpu);
794845
if (ret) {

‎include/zephyr/drivers/clock_control/esp32_clock_control.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
2+
* Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -19,6 +19,8 @@
1919
#include <zephyr/dt-bindings/clock/esp32c3_clock.h>
2020
#elif defined(CONFIG_SOC_SERIES_ESP32C6)
2121
#include <zephyr/dt-bindings/clock/esp32c6_clock.h>
22+
#elif defined(CONFIG_SOC_SERIES_ESP32H2)
23+
#include <zephyr/dt-bindings/clock/esp32h2_clock.h>
2224
#endif /* CONFIG_SOC_SERIES_ESP32xx */
2325

2426
#define ESP32_CLOCK_CONTROL_SUBSYS_CPU 50

‎include/zephyr/dt-bindings/clock/esp32h2_clock.h

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
1+
/*
2+
* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32H2_H_
8+
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32H2_H_
9+
10+
/* Supported CPU clock Sources */
11+
#define ESP32_CPU_CLK_SRC_XTAL 0U
12+
#define ESP32_CPU_CLK_SRC_PLL 1U
13+
#define ESP32_CLK_SRC_RC_FAST 2U
14+
#define ESP32_CPU_CLK_SRC_FLASH_PLL 3U
15+
16+
/* Supported CPU frequencies */
17+
#define ESP32_CLK_CPU_PLL_48M 48000000
18+
#define ESP32_CLK_CPU_FLASH_PLL_64M 64000000
19+
#define ESP32_CLK_CPU_PLL_96M 96000000
20+
#define ESP32_CLK_CPU_RC_FAST_FREQ 8500000
21+
22+
/* Supported XTAL Frequencies */
23+
#define ESP32_CLK_XTAL_32M 32000000
24+
25+
/* Supported RTC fast clock sources */
26+
#define ESP32_RTC_FAST_CLK_SRC_RC_FAST 0
27+
#define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 1
28+
29+
/* Supported RTC slow clock frequencies */
30+
#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0
31+
#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1
32+
#define ESP32_RTC_SLOW_CLK_SRC_RC32K 2
33+
#define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9
34+
35+
/* RTC slow clock frequencies */
36+
#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000
37+
#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768
38+
#define ESP32_RTC_SLOW_CLK_SRC_RC32K_FREQ 32768
39+
40+
/* Modules IDs
41+
* These IDs are actually offsets in CLK and RST Control registers.
42+
* These IDs shouldn't be changed unless there is a Hardware change
43+
* from Espressif.
44+
*
45+
* Basic Modules
46+
* Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
47+
*/
48+
#define ESP32_LEDC_MODULE 0
49+
#define ESP32_UART0_MODULE 1
50+
#define ESP32_UART1_MODULE 2
51+
#define ESP32_USB_DEVICE_MODULE 3
52+
#define ESP32_I2C0_MODULE 4
53+
#define ESP32_I2C1_MODULE 5
54+
#define ESP32_I2S1_MODULE 6
55+
#define ESP32_TIMG0_MODULE 7
56+
#define ESP32_TIMG1_MODULE 8
57+
#define ESP32_UHCI0_MODULE 9
58+
#define ESP32_RMT_MODULE 10
59+
#define ESP32_PCNT_MODULE 11
60+
#define ESP32_SPI_MODULE 12
61+
#define ESP32_SPI2_MODULE 13
62+
#define ESP32_TWAI0_MODULE 14
63+
#define ESP32_RNG_MODULE 15
64+
#define ESP32_RSA_MODULE 16
65+
#define ESP32_AES_MODULE 17
66+
#define ESP32_SHA_MODULE 18
67+
#define ESP32_ECC_MODULE 19
68+
#define ESP32_HMAC_MODULE 20
69+
#define ESP32_DS_MODULE 21
70+
#define ESP32_ECDSA_MODULE 22
71+
#define ESP32_GDMA_MODULE 23
72+
#define ESP32_MCPWM0_MODULE 24
73+
#define ESP32_ETM_MODULE 25
74+
#define ESP32_PARLIO_MODULE 26
75+
#define ESP32_SYSTIMER_MODULE 27
76+
#define ESP32_SARADC_MODULE 28
77+
#define ESP32_TEMPSENSOR_MODULE 29
78+
#define ESP32_REGDMA_MODULE 30
79+
/* Peripherals clock managed by the modem_clock driver must be listed last */
80+
#define ESP32_BT_MODULE 31
81+
#define ESP32_IEEE802154_MODULE 32
82+
#define ESP32_COEX_MODULE 33
83+
#define ESP32_PHY_MODULE 34
84+
#define ESP32_ANA_I2C_MASTER_MODULE 35
85+
#define ESP32_MODEM_ETM_MODULE 36
86+
#define ESP32_MODEM_ADC_COMMON_FE_MODULE 37
87+
#define ESP32_MODULE_MAX 38
88+
89+
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32H2_H_ */

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