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Nicolas Pitre
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boards: arm: fvp: Add Cortex-A320 board variant support
Add Cortex-A320 support to the unified FVP board structure with ARMv9.2-A specific configuration parameters. Signed-off-by: Nicolas Pitre <[email protected]>
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‎arch/arm64/core/Kconfig‎

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@@ -89,6 +89,16 @@ config CPU_CORTEX_A510
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power-efficient processing optimized for embedded applications with
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ARMv9-A features.
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config CPU_CORTEX_A320
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bool
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select CPU_CORTEX_A
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select ARMV9_A
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help
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This option signifies the use of a Cortex-A320 CPU, which implements
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the ARMv9.2-A architecture. It provides advanced features including
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enhanced SVE2, improved security extensions, and specialized performance
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optimizations.
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config CPU_CORTEX_R82
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bool
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select CPU_AARCH64_CORTEX_R

‎boards/arm/fvp_base_revc_2xaem/Kconfig.fvp_base_revc_2xaem‎

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@@ -26,3 +26,8 @@ config BOARD_FVP_BASE_REVC_2XAEM_V9A_SMP
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bool
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default y if BOARD_QUALIFIERS = "v9a/smp" || BOARD_QUALIFIERS = "v9a/smp/ns"
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select BOARD_FVP_BASE_REVC_2XAEM_V9A
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config BOARD_FVP_BASE_REVC_2XAEM_A320
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bool
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default y if BOARD_QUALIFIERS = "a320"
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select SOC_FVP_A320

‎boards/arm/fvp_base_revc_2xaem/board.cmake‎

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@@ -50,6 +50,87 @@ if(CONFIG_ARMV9_A)
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set(ARMFVP_MIN_VERSION 11.29.27)
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endif()
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# Add Cortex-A320 specific configuration flags
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if(CONFIG_BOARD_FVP_BASE_REVC_2XAEM_A320)
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set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
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# Cortex-A320 specific CPU identification
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-C cluster0.MIDR=0x410FD8F0
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-C cluster0.AMIIDR=0xD8F0043B
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-C cluster0.AMPIDR=0x4000BBD8F
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-C cluster0.ERRIIDR=0xD8F0043B
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-C cluster0.ERRPIDR=0x4000BBD8F
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-C cluster0.PMUPIDR=0x4000BBD80
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-C cluster0.CTIPIDR=0x4003BBD8F
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-C cluster0.DBGPIDR=0x4003BBD8F
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# ARMv9.2-A support level
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-C cluster0.has_arm_v9-2=1
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# Advanced SIMD and crypto support
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-C cluster0.advsimd_bf16_support_level=1
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-C cluster0.advsimd_i8mm_support_level=1
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-C cluster0.cpu0.crypto_sha3=1
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-C cluster0.cpu0.crypto_sha512=1
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-C cluster0.cpu0.crypto_sm3=1
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-C cluster0.cpu0.crypto_sm4=1
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-C cluster0.cpu0.enable_crc32=1
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# Memory tagging support
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-C cluster0.memory_tagging_support_level=3
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# Enhanced security features
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-C cluster0.has_qarma3_pac=1
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-C cluster0.has_const_pac=2
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# SVE configuration for Cortex-A320
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-C cluster0.sve.veclen=2
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# Performance monitoring
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-C cluster0.pmu-num_counters=6
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-C cluster0.configure_pmu_events_with_json='{"pmu_events":["SVE_INST_RETIRED","BR_INDNR_TAKEN_RETIRED","BR_IND_RETIRED","EXC_IRQ","EXC_FIQ","EXC_RETURN","EXC_TAKEN","L1D_CACHE_RD","L2D_CACHE_RD","BUS_ACCESS_RD","BUS_ACCESS_WR","MEM_ACCESS_RD","MEM_ACCESS_WR","BR_PRED_RETIRED","BR_IMMED_MIS_PRED_RETIRED","BR_IND_MIS_PRED_RETIRED","BR_RETURN_PRED_RETIRED","BR_RETURN_MIS_PRED_RETIRED","BR_INDNR_PRED_RETIRED","BR_INDNR_MIS_PRED_RETIRED","BR_IMMED_PRED_RETIRED"]}'
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# Cache configuration
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-C cluster0.dcache-ways=4
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-C cluster0.icache-ways=4
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-C cluster0.l2cache-ways=8
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-C cluster0.icache-log2linelen=6
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-C cluster0.l2cache-read_bus_width_in_bytes=16
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-C cluster0.l2cache-write_bus_width_in_bytes=32
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# Debug and trace configuration
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-C cluster0.has_ets=1
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-C cluster0.has_trbe=1
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-C cluster0.has_self_hosted_trace_extension=2
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# Advanced architectural features
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-C cluster0.has_ccidx=1
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-C cluster0.has_16k_granule=1
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-C cluster0.ecv_support_level=2
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-C cluster0.has_cvadp_support=1
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-C cluster0.has_lrcpc=1
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-C cluster0.has_dot_product=2
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-C cluster0.has_wfet_and_wfit=2
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-C cluster0.has_xs=2
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-C cluster0.has_v8_5_debug_over_power_down=2
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-C cluster0.has_v8_7_fp_enhancements=2
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-C cluster0.has_amu=1
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-C cluster0.has_mpmm=1
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-C cluster0.has_mpam=2
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-C cluster0.has_ras=2
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# Memory system configuration
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-C cluster0.stage12_tlb_size=1024
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-C cluster0.restriction_on_speculative_execution=2
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-C cluster0.restriction_on_speculative_execution_aarch32=2
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# Error handling
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-C cluster0.number_of_error_records=3
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-C cluster0.ERXMISC0_mask=0xC003FFC3
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)
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# Set minimum FVP version for Cortex-A320 features
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set(ARMFVP_MIN_VERSION 11.29.27)
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endif()
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if(CONFIG_BUILD_WITH_TFA)
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set(TFA_PLAT "fvp")
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‎boards/arm/fvp_base_revc_2xaem/board.yml‎

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@@ -13,3 +13,4 @@ board:
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- name: smp
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variants:
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- name: ns
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- name: a320

‎boards/arm/fvp_base_revc_2xaem/doc/index.rst‎

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@@ -49,6 +49,18 @@ This board configuration supports multiple architecture variants:
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* ``fvp_base_revc_2xaem/v9a`` - ARMv9-A (64-bit) with Cortex-A510 cores
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* ``fvp_base_revc_2xaem/v9a/smp`` - ARMv9-A SMP (4 cores)
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* ``fvp_base_revc_2xaem/v9a/smp/ns`` - ARMv9-A SMP Non-Secure
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* ``fvp_base_revc_2xaem/a320`` - ARMv9.2-A with Cortex-A320 configuration
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**Cortex-A320 Configuration:**
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The ``a320`` variant provides Cortex-A320 specific FVP configuration with:
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* ARMv9.2-A architecture compliance
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* Enhanced cryptographic extensions (SHA3, SHA512, SM3, SM4)
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* Advanced memory tagging (MTE Level 3)
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* QARMA3 Pointer Authentication
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* Optimized cache configuration for Cortex-A320
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* Performance monitoring unit with SVE-specific events
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Devices
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========
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:board: fvp_base_revc_2xaem/v9a
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:goals: build
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For Cortex-A320 specific configuration:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:host-os: unix
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:board: fvp_base_revc_2xaem/a320
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:goals: build
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For SMP variants:
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.. zephyr-app-commands::

‎boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_a320.dts‎

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/*
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* Copyright (c) 2025 BayLibre SAS
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <arm64/armv9-a.dtsi>
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#include "fvp_base_revc_2xaem.dtsi"
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/ {
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model = "FVP Base RevC 2xAEMv9A (Cortex-A320)";
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};
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&cpu0 {
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compatible = "arm,cortex-a320";
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};
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&cpu1 {
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compatible = "arm,cortex-a320";
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};
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&cpu2 {
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compatible = "arm,cortex-a320";
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};
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&cpu3 {
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compatible = "arm,cortex-a320";
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};

‎boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_a320.yaml‎

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# Copyright (c) 2025 BayLibre SAS
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# SPDX-License-Identifier: Apache-2.0
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identifier: fvp_base_revc_2xaem/a320
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name: FVP Emulation FVP_Base_RevC-2xAEMv9A (Cortex-A320)
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arch: arm64
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type: sim
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simulation:
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- name: armfvp
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exec: FVP_Base_RevC-2xAEMvA
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toolchain:
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- zephyr
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- cross-compile
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ram: 2048
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flash: 64
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vendor: arm

‎boards/arm/fvp_base_revc_2xaem/fvp_base_revc_2xaem_a320_defconfig‎

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# Copyright (c) 2025 BayLibre SAS
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_XIP=n
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CONFIG_THREAD_STACK_INFO=y
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# Enable Timer and Sys clock
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CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
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CONFIG_ARM_ARCH_TIMER=y
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# Enable UART driver
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CONFIG_SERIAL=y
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# Enable serial port
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CONFIG_UART_INTERRUPT_DRIVEN=y
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# Enable console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y

‎cmake/gcc-m-cpu.cmake‎

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set(GCC_M_CPU cortex-a78)
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elseif(CONFIG_CPU_CORTEX_A510)
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set(GCC_M_CPU cortex-a510)
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elseif(CONFIG_CPU_CORTEX_A320)
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# Cortex-A320 was announced in February 2025 and is not yet supported in any GCC version
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# Use cortex-a710 as fallback since both are high-performance ARMv9-A cores with similar features
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# TODO: Update to use cortex-a320 when GCC support is added (likely in GCC 15 or 16)
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set(GCC_M_CPU cortex-a710)
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message(STATUS "Using cortex-a710 as fallback for cortex-a320 (not yet supported in GCC)")
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elseif(CONFIG_CPU_CORTEX_R82)
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set(GCC_M_CPU cortex-r82)
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endif()

‎dts/bindings/cpu/arm,cortex-a320.yaml‎

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# Copyright (c) 2025 BayLibre SAS
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# SPDX-License-Identifier: Apache-2.0
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description: ARM Cortex-A320 CPU
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compatible: "arm,cortex-a320"
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include: cpu.yaml

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