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nzmichaelhDhiru Kholia
nzmichaelh
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Dhiru Kholia
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drivers: add the ch32v00x usart driver
This commit adds the usart driver for WCH CH32V003. Signed-off-by: Michael Hope <[email protected]> Signed-off-by: Dhiru Kholia <[email protected]>
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‎drivers/serial/CMakeLists.txt‎

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@@ -73,6 +73,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_STELLARIS uart_stellaris.c)
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zephyr_library_sources_ifdef(CONFIG_UART_STM32 uart_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SY1XX uart_sy1xx.c)
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zephyr_library_sources_ifdef(CONFIG_UART_TELINK_B91 uart_b91.c)
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zephyr_library_sources_ifdef(CONFIG_UART_WCH_USART uart_wch_usart.c)
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zephyr_library_sources_ifdef(CONFIG_UART_XEC uart_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_UART_XEN_HVC uart_hvc_xen.c)
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zephyr_library_sources_ifdef(CONFIG_UART_XEN_HVC_CONSOLEIO uart_hvc_xen_consoleio.c)

‎drivers/serial/Kconfig‎

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@@ -221,4 +221,6 @@ rsource "Kconfig.xmc4xxx"
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source "drivers/serial/Kconfig.si32"
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source "drivers/serial/Kconfig.wch_usart"
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endif # SERIAL

‎drivers/serial/Kconfig.wch_usart‎

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# Copyright (c) 2024 Google LLC.
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# SPDX-License-Identifier: Apache-2.0
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config UART_WCH_USART
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bool "CH32V00x USART driver"
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default y
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depends on DT_HAS_WCH_USART_ENABLED
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select SERIAL_HAS_DRIVER
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help
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This option enables the USART driver for CH32V00x SoC family.

‎drivers/serial/uart_wch_usart.c‎

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/*
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* Copyright (c) 2024 Google LLC.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT wch_usart
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#include <errno.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <ch32_uart.h>
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struct usart_wch_config {
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USART_TypeDef *regs;
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const struct device *clock_dev;
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uint32_t current_speed;
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uint8_t parity;
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uint8_t clock_id;
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const struct pinctrl_dev_config *pin_cfg;
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};
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struct usart_wch_data {
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};
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static int usart_wch_init(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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uint32_t ctlr1 = USART_CTLR1_TE | USART_CTLR1_RE | USART_CTLR1_UE;
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uint32_t clock_rate;
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clock_control_subsys_t clock_sys = (clock_control_subsys_t *)(uintptr_t)config->clock_id;
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uint32_t divn;
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int err;
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clock_control_on(config->clock_dev, clock_sys);
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err = clock_control_get_rate(config->clock_dev, clock_sys, &clock_rate);
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if (err != 0) {
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return err;
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}
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divn = (clock_rate + config->current_speed / 2) / config->current_speed;
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switch (config->parity) {
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case UART_CFG_PARITY_NONE:
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break;
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case UART_CFG_PARITY_ODD:
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ctlr1 |= USART_CTLR1_PCE | USART_CTLR1_PS;
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break;
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case UART_CFG_PARITY_EVEN:
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ctlr1 |= USART_CTLR1_PCE;
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break;
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default:
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return -EINVAL;
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}
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regs->BRR = divn;
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regs->CTLR1 = ctlr1;
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regs->CTLR2 = 0;
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regs->CTLR3 = 0;
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err = pinctrl_apply_state(config->pin_cfg, PINCTRL_STATE_DEFAULT);
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if (err != 0) {
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return err;
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}
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return 0;
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}
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static int usart_wch_poll_in(const struct device *dev, unsigned char *ch)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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if ((regs->STATR & USART_STATR_RXNE) == 0) {
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return -1;
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}
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*ch = regs->DATAR;
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return 0;
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}
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static void usart_wch_poll_out(const struct device *dev, unsigned char ch)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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while ((regs->STATR & USART_STATR_TXE) == 0) {
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}
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regs->DATAR = ch;
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}
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static int usart_wch_err_check(const struct device *dev)
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{
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const struct usart_wch_config *config = dev->config;
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USART_TypeDef *regs = config->regs;
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uint32_t statr = regs->STATR;
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enum uart_rx_stop_reason errors = 0;
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if ((statr & USART_STATR_PE) != 0) {
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errors |= UART_ERROR_PARITY;
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}
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if ((statr & USART_STATR_FE) != 0) {
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errors |= UART_ERROR_FRAMING;
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}
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if ((statr & USART_STATR_NE) != 0) {
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errors |= UART_ERROR_NOISE;
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}
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if ((statr & USART_STATR_ORE) != 0) {
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errors |= UART_ERROR_OVERRUN;
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}
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return errors;
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}
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static const struct uart_driver_api usart_wch_driver_api = {
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.poll_in = usart_wch_poll_in,
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.poll_out = usart_wch_poll_out,
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.err_check = usart_wch_err_check,
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};
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#define USART_WCH_INIT(idx) \
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PINCTRL_DT_INST_DEFINE(idx); \
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static struct usart_wch_data usart_wch_##idx##_data; \
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static const struct usart_wch_config usart_wch_##idx##_config = { \
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.regs = (USART_TypeDef *)DT_INST_REG_ADDR(idx), \
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.current_speed = DT_INST_PROP(idx, current_speed), \
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.parity = DT_INST_ENUM_IDX_OR(idx, parity, UART_CFG_PARITY_NONE), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
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.clock_id = DT_INST_CLOCKS_CELL(idx, id), \
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.pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
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}; \
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DEVICE_DT_INST_DEFINE(idx, &usart_wch_init, NULL, &usart_wch_##idx##_data, \
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&usart_wch_##idx##_config, PRE_KERNEL_1, \
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CONFIG_SERIAL_INIT_PRIORITY, &usart_wch_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(USART_WCH_INIT)

‎dts/bindings/serial/wch,usart.yaml‎

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description: WCH CH32V00x UART
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compatible: "wch,usart"
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include: [uart-controller.yaml, pinctrl-device.yaml]
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properties:
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reg:
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required: true

‎modules/hal_wch/ch32_uart.h‎

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/*
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* Copyright (c) 2024 Dhiru Kholia
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _CH32_UART_H
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#define _CH32_UART_H
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#ifdef CONFIG_SOC_CH32V003
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#include <ch32v003fun.h>
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#else
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#error "SoC not supported!"
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#endif
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#endif

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