drivers: can: STM32H7 in can_mcan_reg, clock config.

* Add STM32h7 fields to can_mcan_reg.
* STM32H FDCAN clock config changes.

Signed-off-by: Jeremy Wood <[email protected]>

Author: JeremyBCD

drivers/can/can_mcan_int.h

@@ -1478,14 +1478,33 @@ struct can_mcan_reg {
 	volatile uint32_t ile;      /* Interrupt Line Enable */
 	uint32_t res3[8];           /* Reserved (8) */
 	volatile uint32_t rxgfc;    /* Global Filter Configuration */
+#if defined(CONFIG_SOC_SERIES_STM32H7X)
+	volatile uint32_t sidfc;     /* Standard ID Filter Configuration */
+	volatile uint32_t xidfc;     /* Extended ID Filter Configuration */
+	uint32_t res31;              /* Reserved (1) */
+#endif  /* CONFIG_SOC_SERIES_STM32H7X */
 	volatile uint32_t xidam;    /* Extended ID AND Mask */
 	volatile uint32_t hpms;     /* High Priority Message Status */
+#if defined(CONFIG_SOC_SERIES_STM32H7X)
+	volatile uint32_t ndat1;     /* New Data 1 */
+	volatile uint32_t ndat2;     /* New Data 2 */
+	volatile uint32_t rxf0c;     /* Rx FIFO 0 Configuration */
+#else
 	uint32_t res4;              /* Reserved (1) */
+#endif  /* CONFIG_SOC_SERIES_STM32H7X */
 	volatile uint32_t rxf0s;    /* Rx FIFO 0 Status */
 	volatile uint32_t rxf0a;    /* Rx FIFO 0 Acknowledge */
+#if defined(CONFIG_SOC_SERIES_STM32H7X)
+	volatile uint32_t rxbc;     /* Rx Buffer Configuration */
+	volatile uint32_t rxf1c;    /* Rx FIFO 1 Configuration */
+#endif  /* CONFIG_SOC_SERIES_STM32H7X */
 	volatile uint32_t rxf1s;    /* Rx FIFO 1 Status */
 	volatile uint32_t rxf1a;    /* Rx FIFO 1 Acknowledge */
+#if defined(CONFIG_SOC_SERIES_STM32H7X)
+	volatile uint32_t rxesc;    /* Rx Buffer/FIFO Element Size Configuration */
+#else
 	uint32_t res5[8];           /* Reserved (8) */
+#endif  /* CONFIG_SOC_SERIES_STM32H7X */
 	volatile uint32_t txbc;     /* Tx Buffer Configuration */
 	volatile uint32_t txfqs;    /* Tx FIFO/Queue Status */
 	volatile uint32_t txbrp;    /* Tx Buffer Request Pending */
@@ -1495,8 +1514,15 @@ struct can_mcan_reg {
 	volatile uint32_t txbcf;    /* Tx Buffer Cancellation Finished */
 	volatile uint32_t txbtie;   /* Tx Buffer Transmission Interrupt Enable */
 	volatile uint32_t txcbie;   /* Tx Buffer Cancellation Fi.Interrupt En. */
+#if defined(CONFIG_SOC_SERIES_STM32H7X)
+	uint32_t res5[2];           /* Reserved (2) */
+	volatile uint32_t txefc;   /* Tx Event FIFO Configuration */
+#endif  /* CONFIG_SOC_SERIES_STM32H7X */
 	volatile uint32_t txefs;    /* Tx Event FIFO Status */
 	volatile uint32_t txefa;    /* Tx Event FIFO Acknowledge */
+#if defined(CONFIG_SOC_SERIES_STM32H7X)
+	uint32_t res6;              /* Reserved (1) */
+#endif  /* CONFIG_SOC_SERIES_STM32H7X */
 };
 #else /* CONFIG_CAN_STM32FD */
 

drivers/can/can_stm32fd.c

@@ -40,10 +40,19 @@ int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate)
 
 void can_stm32fd_clock_enable(void)
 {
+#if defined(CONFIG_SOC_SERIES_STM32H7X)
+	LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PLL1Q);
+	__HAL_RCC_FDCAN_CLK_ENABLE();
+
+	if (!LL_RCC_PLL1Q_IsEnabled()) {
+		LOG_ERR("PLL1Q clock must be enabled!");
+	}
+#else
 	LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1);
 	__HAL_RCC_FDCAN_CLK_ENABLE();
 
 	FDCAN_CONFIG->CKDIV = CONFIG_CAN_STM32_CLOCK_DIVISOR >> 1;
+#endif
 }
 
 void can_stm32fd_register_state_change_isr(const struct device *dev,