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drivers: pinctrl: Add support for RZ/N2L
This is the initial commit to support pinctrl driver for Renesas RZ/N2L Signed-off-by: Hoang Nguyen <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>
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‎boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzn-common.h>
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&pinctrl {
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/omit-if-no-ref/ sci0_default: sci0_default {
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sci0-pinmux {
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pinmux = <RZN_PINMUX(PORT_16, 5, 1)>, /* TXD */
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<RZN_PINMUX(PORT_16, 6, 2)>; /* RXD */
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};
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};
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/omit-if-no-ref/ sci3_default: sci3_default {
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sci3-pinmux {
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pinmux = <RZN_PINMUX(PORT_18, 0, 4)>, /* TXD */
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<RZN_PINMUX(PORT_17, 7, 4)>; /* RXD */
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};
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};
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/omit-if-no-ref/ irq7_default: irq7_default {
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irq7-pinmux {
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pinmux = <RZN_PINMUX(PORT_16, 3, 0)>;
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input-enable;
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};
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};
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};

‎drivers/pinctrl/renesas/rz/Kconfig

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config PINCTRL_RENESAS_RZ
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bool "Renesas RZ pin controller driver"
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default y
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depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED
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depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED || DT_HAS_RENESAS_RZN_PINCTRL_ENABLED
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select USE_RZ_FSP_IOPORT
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help
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Enable Renesas RZ pinctrl driver.

‎dts/arm/renesas/rz/rzn/r9a07g084.dtsi

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};
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};
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};
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pinctrl: pinctrl@800a0000 {
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compatible = "renesas,rzn-pinctrl";
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reg = <0x800a0000 0x1000 0x81030c00 0x1000>;
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};
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};
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};

‎dts/bindings/pinctrl/renesas,rzn-pinctrl.yaml

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: |
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The Renesas RZ/N2L pin controller is a node responsible for controlling
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pin function selection and pin properties, such as routing the TX and RX of UART0
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to pin 5 and pin 6 of port 16.
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The node has the 'pinctrl' node label set in your SoC's devicetree,
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so you can modify it like this:
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&pinctrl {
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/* your modifications go here */
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};
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All device pin configurations should be placed in child nodes of the
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'pinctrl' node, as shown in this example:
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/* You can put this in places like a board-pinctrl.dtsi file in
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* your board directory, or a devicetree overlay in your application.
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*/
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/* include pre-defined combinations for the SoC variant used by the board */
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzn-common.h>
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&pinctrl {
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uart0_pins: uart0 {
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group1 {
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pinmux = <RZN_PINMUX(PORT_16, 5, 1)>; /* TXD */
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};
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group2 {
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pinmux = <RZN_PINMUX(PORT_16, 6, 2)>; /* RXD */
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input-enable;
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};
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};
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};
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The 'uart0_pins' child node encodes the pin configurations for a
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particular state of a device; in this case, the default (that is, active)
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state.
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As shown, pin configurations are organized in groups within each child node.
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Each group can specify a list of pin function selections in the 'pinmux'
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property.
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A group can also specify shared pin properties common to all the specified
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pins, such as the 'input-enable' property in group 2.
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compatible: "renesas,rzn-pinctrl"
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include: base.yaml
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child-binding:
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description: |
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Definitions for a pinctrl state.
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child-binding:
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- input-enable
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- output-enable
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- output-high
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- bias-pull-up
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- bias-pull-down
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- input-schmitt-enable
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properties:
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pinmux:
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required: true
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type: array
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description: |
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An array of pins sharing the same group properties. Each
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element of the array is an integer constructed from the
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pin number and the alternative function of the pin.
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drive-strength:
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type: string
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enum:
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- "low"
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- "middle"
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- "high"
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- "ultrahigh"
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default: "low"
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description: |
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The drive strength of a pin, relative to full-driver strength.
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The default value is "low", which is the reset value.
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slew-rate:
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type: string
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enum:
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- "slow"
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- "fast"
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default: "slow"
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description: |
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Select slew rate for a pin. The default is slow, which is the reset value.

‎include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzn-common.h

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZN_COMMON_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZN_COMMON_H_
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/* Superset list of all possible IO ports. */
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#define PORT_00 0x0000 /* IO port 0 */
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#define PORT_01 0x0100 /* IO port 1 */
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#define PORT_02 0x0200 /* IO port 2 */
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#define PORT_03 0x0300 /* IO port 3 */
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#define PORT_04 0x0400 /* IO port 4 */
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#define PORT_05 0x0500 /* IO port 5 */
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#define PORT_06 0x0600 /* IO port 6 */
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#define PORT_07 0x0700 /* IO port 7 */
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#define PORT_08 0x0800 /* IO port 8 */
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#define PORT_09 0x0900 /* IO port 9 */
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#define PORT_10 0x0A00 /* IO port 10 */
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#define PORT_11 0x0B00 /* IO port 11 */
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#define PORT_12 0x0C00 /* IO port 12 */
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#define PORT_13 0x0D00 /* IO port 13 */
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#define PORT_14 0x0E00 /* IO port 14 */
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#define PORT_15 0x0F00 /* IO port 15 */
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#define PORT_16 0x1000 /* IO port 16 */
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#define PORT_17 0x1100 /* IO port 17 */
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#define PORT_18 0x1200 /* IO port 18 */
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#define PORT_19 0x1300 /* IO port 19 */
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#define PORT_20 0x1400 /* IO port 20 */
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#define PORT_21 0x1500 /* IO port 21 */
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#define PORT_22 0x1600 /* IO port 22 */
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#define PORT_23 0x1700 /* IO port 23 */
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#define PORT_24 0x1800 /* IO port 24 */
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/*
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* Create the value contain port/pin/function information
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*
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* port: port number BSP_IO_PORT_00..BSP_IO_PORT_34
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* pin: pin number
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* func: pin function
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*/
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#define RZN_PINMUX(port, pin, func) (port | pin | (func << 4))
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZN_COMMON_H_ */

‎soc/renesas/rz/common/pinctrl_rzn.h

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZN_H_
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#define ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZN_H_
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#include <zephyr/types.h>
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#include <zephyr/devicetree.h>
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#include "r_ioport.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define RZN_GET_PORT_PIN(pinmux) (pinmux & ~(0xF << 4))
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#define RZN_GET_FUNC(pinmux) ((pinmux & 0xF0) >> 4)
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/* Porting */
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typedef struct pinctrl_cfg_data_t {
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uint32_t p_reg: 1;
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uint32_t pm_reg: 2;
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uint32_t pmc_reg: 1;
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uint32_t pfc_reg: 4;
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uint32_t drct_reg: 6;
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uint32_t rsel_reg: 1;
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uint32_t reserved: 17;
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} pinctrl_cfg_data_t;
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typedef struct pinctrl_soc_pin_t {
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bsp_io_port_pin_t port_pin;
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pinctrl_cfg_data_t config;
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} pinctrl_soc_pin_t;
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
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{ \
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.port_pin = RZN_GET_PORT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)), \
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.config = \
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{ \
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.p_reg = DT_PROP(node_id, output_high), \
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.pm_reg = DT_PROP(node_id, input_enable) == 1 \
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? 1U \
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: (DT_PROP(node_id, output_enable) == 1 ? 2U \
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: 0U), \
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.pmc_reg = 1, \
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.pfc_reg = RZN_GET_FUNC(DT_PROP_BY_IDX(node_id, prop, idx)), \
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.drct_reg = \
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(DT_ENUM_IDX(node_id, drive_strength)) | \
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((DT_PROP(node_id, bias_pull_up) == 1 \
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? 1U \
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: (DT_PROP(node_id, bias_pull_down) == 1 ? 2U \
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: 0)) \
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<< 2) | \
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(DT_PROP(node_id, input_schmitt_enable) << 4) | \
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(DT_ENUM_IDX(node_id, slew_rate) << 5), \
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.rsel_reg = 1, \
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.reserved = 0, \
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}, \
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},
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
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Z_PINCTRL_STATE_PIN_INIT)}
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZN_H_ */

‎soc/renesas/rz/rzn2l/pinctrl_soc.h

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RZ_RZN2L_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_RENESAS_RZ_RZN2L_PINCTRL_SOC_H_
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#include <pinctrl_rzn.h>
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#endif /* ZEPHYR_SOC_RENESAS_RZ_RZN2L_PINCTRL_SOC_H_ */

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