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soc: nxp mcxc: Add support for NXP MCXC series
Add initial suport for NXP MCXC series Signed-off-by: Michal Smola <[email protected]>
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‎soc/nxp/mcx/mcxc/CMakeLists.txt‎

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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources_ifdef(CONFIG_MCXC_FLASH_CONFIG flash_configuration.c)
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zephyr_include_directories(.)
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zephyr_sources(soc.c)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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zephyr_linker_sources_ifdef(CONFIG_MCXC_FLASH_CONFIG
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ROM_START
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SORT_KEY ${CONFIG_MCXC_FLASH_CONFIG_OFFSET}
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flash_config.ld
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)
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# CMSIS SystemInit will disable watchdog unless instructed not to.
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# Add a compiler definition here to leave watchdog untouched
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# if this Kconfig is set
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zephyr_compile_definitions_ifdef(CONFIG_WDOG_ENABLE_AT_BOOT DISABLE_WDOG=0)

‎soc/nxp/mcx/mcxc/Kconfig‎

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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_MCXC
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select ARM
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select CLOCK_CONTROL
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select PLATFORM_SPECIFIC_INIT
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select HAS_MCUX
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select HAS_MCUX_ADC16
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select HAS_MCUX_SIM
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select HAS_MCUX_RCM
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select HAS_MCUX_FTFX
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select HAS_MCUX_LPUART
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select HAS_MCUX_LPI2C
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select HAS_MCUX_TPM
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if SOC_SERIES_MCXC
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config MCXC_FLASH_CONFIG
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bool "MCXC flash configuration field"
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default y if XIP && !BOOTLOADER_MCUBOOT
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help
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Include the 16-byte flash configuration field that stores default
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protection settings (loaded on reset) and security information that
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allows the MCU to restrict access to the FTFx module.
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if MCXC_FLASH_CONFIG
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config MCXC_FLASH_CONFIG_OFFSET
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hex
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default $(dt_node_int_prop_hex,/soc/flash-controller@40020000,config-field-offset)
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endif # MCXC_FLASH_CONFIG
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config WDOG_ENABLE_AT_BOOT
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bool "Keep watchdog timer enabled at boot"
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help
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Leave SOC watchdog timer enabled at boot. The specific timeout
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and clock configuration of the watchdog at boot is SOC dependent.
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Note: if the watchdog timer is enabled at boot, the user will
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need to configure the watchdog using z_arm_watchdog_init, as
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the SOC requires watchdog configuration before initial expiration
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# Enable watchdog configuration function if watchdog is left enabled at boot
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config WDOG_INIT
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bool
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default WDOG_ENABLE_AT_BOOT
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endif # SOC_FAMILY_MCXC

‎soc/nxp/mcx/mcxc/Kconfig.defconfig‎

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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_MCXC
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config NUM_IRQS
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default 32
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 48000000
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endif # SOC_SERIES_MCXC

‎soc/nxp/mcx/mcxc/Kconfig.soc‎

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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_MCXC
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bool
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select SOC_FAMILY_NXP_MCX
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config SOC_SERIES
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default "mcxc" if SOC_SERIES_MCXC
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config SOC_MCXC141
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bool
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select SOC_SERIES_MCXC
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config SOC_MCXC142
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bool
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select SOC_SERIES_MCXC
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config SOC_MCXC242
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bool
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select SOC_SERIES_MCXC
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config SOC
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default "mcxc141" if SOC_MCXC141
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default "mcxc142" if SOC_MCXC142
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default "mcxc242" if SOC_MCXC242
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config SOC_PART_NUMBER_MCXC141VLH
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bool
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config SOC_PART_NUMBER_MCXC141VFM
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bool
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config SOC_PART_NUMBER_MCXC142VFM
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bool
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config SOC_PART_NUMBER_MCXC242VLH
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bool
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config SOC_PART_NUMBER_MCXC242VFM
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bool
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config SOC_PART_NUMBER
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default "MCXC141VFM" if SOC_PART_NUMBER_MCXC141VLH
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default "MCXC141VFM" if SOC_PART_NUMBER_MCXC141VFM
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default "MCXC141VFM" if SOC_PART_NUMBER_MCXC142VFM
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default "MCXC242VLH" if SOC_PART_NUMBER_MCXC242VLH
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default "MCXC242VFM" if SOC_PART_NUMBER_MCXC242VFM

‎soc/nxp/mcx/mcxc/flash_config.ld‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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. = DT_PROP(DT_NODELABEL(ftfa), config_field_offset);
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KEEP(*(.kinetis_flash_config))
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KEEP(*(".kinetis_flash_config.*"))

‎soc/nxp/mcx/mcxc/flash_configuration.c‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/device.h>
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uint8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
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/* Backdoor Comparison Key (unused) */
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0xFF,
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0xFF,
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0xFF,
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0xFF,
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0xFF,
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0xFF,
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0xFF,
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0xFF,
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/* Program flash protection; 1 bit/region - 0=protected, 1=unprotected
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*/
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0xFF,
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0xFF,
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0xFF,
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0xFF,
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/* Flash security register (FSEC) enables/disables backdoor key access,
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* mass erase, factory access, and flash security
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*/
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DT_PROP_OR(DT_NODELABEL(ftfa), fsec, 0xFF),
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/* Flash nonvolatile option register (FOPT) enables/disables NMI,
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* EzPort, and boot options
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*/
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DT_PROP_OR(DT_NODELABEL(ftfa), fopt, 0xFF),
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/* EEPROM protection register (FEPROT) for FlexNVM devices */
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0xFF,
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/* Data flash protection register (FDPROT) for FlexNVM devices */
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0XFF,
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};

‎soc/nxp/mcx/mcxc/pinctrl_soc.h‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_ARM_NXP_MCXC_COMMON_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_ARM_NXP_MCXC_COMMON_PINCTRL_SOC_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef uint32_t pinctrl_soc_pin_t;
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/* MCXC series does not support open drain. Define macros to have no effect */
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#define PORT_PCR_ODE(x) 0x0
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#define PORT_PCR_ODE_MASK 0x0
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#define Z_PINCTRL_MCXC_PINCFG(node_id) \
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(PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \
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PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \
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PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \
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PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) | \
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PORT_PCR_ODE(DT_PROP(node_id, drive_open_drain)) | \
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PORT_PCR_SRE(DT_ENUM_IDX(node_id, slew_rate)) | \
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PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter)))
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#define Z_PINCTRL_KINETIS_PCR_MASK \
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(PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | PORT_PCR_ODE_MASK | \
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PORT_PCR_PFE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_PE_MASK | \
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PORT_PCR_PS_MASK)
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#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
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DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_MCXC_PINCFG(group),
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
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DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)};
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_SOC_ARM_NXP_MCXC_COMMON_PINCTRL_SOC_H_ */

‎soc/nxp/mcx/mcxc/soc.c‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <fsl_common.h>
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#include <fsl_clock.h>
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#include <zephyr/arch/cpu.h>
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define MCG_NODE DT_NODELABEL(mcg)
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#define OSC_NODE DT_NODELABEL(osc)
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#define SIM_LPUART_CLK_SEL_DISABLED 0U /*!< LPUART clock select: Disabled */
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#define SIM_LPUART_CLK_SEL_IRC48M_CLK 1U /*!< LPUART clock select: IRC48M clock */
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#define SIM_LPUART_CLK_SEL_OSCERCLK_CLK 2U /*!< LPUART clock select: OSCERCLK clock */
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#define SIM_LPUART_CLK_SEL_MCGIRCLK_CLK 3U /*!< LPUART clock select: MCGIRCLK clock */
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#define CLOCK_NODEID(clk) DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
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#define CLOCK_DIVIDER(clk) DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
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#define LPUART_CLOCK_SEL(label) \
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(DT_PHA(DT_NODELABEL(label), clocks, name) == kCLOCK_McgIrc48MClk \
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? SIM_LPUART_CLK_SEL_IRC48M_CLK \
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: DT_PHA(DT_NODELABEL(label), clocks, name) == kCLOCK_Osc0ErClk \
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? SIM_LPUART_CLK_SEL_OSCERCLK_CLK \
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: DT_PHA(DT_NODELABEL(label), clocks, name) == kCLOCK_McgInternalRefClk \
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? SIM_LPUART_CLK_SEL_MCGIRCLK_CLK \
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: SIM_LPUART_CLK_SEL_DISABLED)
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/*******************************************************************************
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* Variables
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******************************************************************************/
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const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = {
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.outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
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.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled */
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.ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock */
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/* Low-frequency Reference Clock Divider */
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.fcrdiv = DT_PROP_OR(MCG_NODE, fcrdiv, 0),
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/* Second Low-frequency Reference Clock Divider */
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.lircDiv2 = DT_PROP_OR(MCG_NODE, lircdiv2, 0),
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.hircEnableInNotHircMode = true, /* HIRC source is enabled */
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};
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const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
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.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
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SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
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};
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const osc_config_t oscConfig_BOARD_BootClockRUN = {
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.freq = DT_PROP(OSC_NODE, clock_frequency),
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.capLoad = 0,
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#if DT_ENUM_HAS_VALUE(OSC_NODE, mode, external)
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.workMode = kOSC_ModeExt,
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#elif DT_ENUM_HAS_VALUE(OSC_NODE, mode, low_power)
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.workMode = kOSC_ModeOscLowPower,
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#elif DT_ENUM_HAS_VALUE(OSC_NODE, mode, high_gain)
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.workMode = kOSC_ModeOscHighGain,
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#else
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#error "An oscillator mode must be defined"
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#endif
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.oscerConfig = {
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.enableMode = kOSC_ErClkEnable,
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}
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};
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static void clock_init(void)
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{
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/* Set the system clock dividers in SIM to safe value. */
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CLOCK_SetSimSafeDivs();
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/* Initializes OSC0 according to board configuration. */
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CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
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CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
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/* Set MCG to HIRC mode. */
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CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
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/* Set the clock configuration in SIM module. */
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CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
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/* Set SystemCoreClock variable. */
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SystemCoreClock = DT_PROP(DT_NODELABEL(cpu0), clock_frequency);
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/* Set LPUART0 clock source. */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart0), okay)
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CLOCK_SetLpuart0Clock(LPUART_CLOCK_SEL(lpuart0));
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#endif
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}
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static int mcxc_init(void)
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{
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clock_init();
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return 0;
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}
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#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
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void z_arm_platform_init(void)
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{
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SystemInit();
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}
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#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
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SYS_INIT(mcxc_init, PRE_KERNEL_1, 0);

‎soc/nxp/mcx/mcxc/soc.h‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC__H_
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#define _SOC__H_
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#include <zephyr/sys/util.h>
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#include <fsl_port.h>
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#define UART0_CLK_SRC kCLOCK_CoreSysClk
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#define PORT_MUX_GPIO kPORT_MuxAsGpio /* GPIO setting for the Port Mux Register */
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#ifndef _ASMLANGUAGE
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#include <fsl_common.h>
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#endif /* !_ASMLANGUAGE */
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#endif /* _SOC__H_ */

‎soc/nxp/mcx/soc.yml‎

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- name: cpu0
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- name: cpu1
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- name: mcxn236
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- name: mcxc
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socs:
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- name: mcxc141
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- name: mcxc142
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- name: mcxc242
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runners:
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run_once:
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'--erase':

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