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drivers: gpio: mspm0: Add a gpio support for MSPM0 family
Add a GPIO driver support for TI MSPM0 SoC family. Signed-off-by: Saravanan Sekar <[email protected]> Signed-off-by: Jackson Farley <[email protected]>
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‎drivers/gpio/CMakeLists.txt

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@@ -61,6 +61,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX_LPC gpio_mcux_lpc.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX_RGPIO gpio_mcux_rgpio.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MFXSTM32L152 gpio_mfxstm32l152.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MMIO32 gpio_mmio32.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MSPM0 gpio_mspm0.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX gpio_nct38xx.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX gpio_nct38xx_port.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX_ALERT gpio_nct38xx_alert.c)

‎drivers/gpio/Kconfig

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@@ -149,6 +149,7 @@ source "drivers/gpio/Kconfig.mcux_rgpio"
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source "drivers/gpio/Kconfig.mec5"
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source "drivers/gpio/Kconfig.mfxstm32l152"
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source "drivers/gpio/Kconfig.mmio32"
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source "drivers/gpio/Kconfig.mspm0"
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source "drivers/gpio/Kconfig.nct38xx"
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source "drivers/gpio/Kconfig.neorv32"
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source "drivers/gpio/Kconfig.npcx"

‎drivers/gpio/Kconfig.mspm0

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# TI MSPM0 GPIO configuration options
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# Copyright (c) 2025 Texas Instruments
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_MSPM0
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bool "TI MSPM0 GPIO driver"
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default y
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depends on DT_HAS_TI_MSPM0_GPIO_ENABLED
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select USE_MSPM0_DL_GPIO
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help
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Enable the TI MSPM0 GPIO driver.

‎drivers/gpio/gpio_mspm0.c

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/*
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* Copyright (c) 2025 Texas Instruments
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* Copyright (c) 2025 Linumiz
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_mspm0_gpio
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/* Zephyr includes */
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/irq.h>
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/* Driverlib includes */
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#include <ti/driverlib/dl_gpio.h>
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struct gpio_mspm0_config {
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/* gpio_mspm0_config needs to be first (doesn't actually get used) */
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struct gpio_driver_config common;
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/* port base address */
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GPIO_Regs *base;
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/* port pincm lookup table */
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uint32_t *pincm_lut;
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};
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struct gpio_mspm0_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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sys_slist_t callbacks; /* List of interrupt callbacks */
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};
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/* Two polarity registers and HAL api used for pins (0-15) and pins (16-32) */
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#define MSPM0_PINS_LOW_GROUP 16
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/* GPIO defines */
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#define GPIOA_NODE DT_NODELABEL(gpioa)
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#if DT_NODE_HAS_STATUS(GPIOA_NODE, okay)
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#if CONFIG_SOC_SERIES_MSPM0G
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#define NUM_GPIOA_PIN 32
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#define gpioa_pins NUM_GPIOA_PIN
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static uint32_t gpioa_pincm_lut[NUM_GPIOA_PIN] = {
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IOMUX_PINCM1, IOMUX_PINCM2, IOMUX_PINCM7, IOMUX_PINCM8, IOMUX_PINCM9, IOMUX_PINCM10,
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IOMUX_PINCM11, IOMUX_PINCM14, IOMUX_PINCM19, IOMUX_PINCM20, IOMUX_PINCM21, IOMUX_PINCM22,
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IOMUX_PINCM34, IOMUX_PINCM35, IOMUX_PINCM36, IOMUX_PINCM37, IOMUX_PINCM38, IOMUX_PINCM39,
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IOMUX_PINCM40, IOMUX_PINCM41, IOMUX_PINCM42, IOMUX_PINCM46, IOMUX_PINCM47, IOMUX_PINCM53,
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IOMUX_PINCM54, IOMUX_PINCM55, IOMUX_PINCM59, IOMUX_PINCM60, IOMUX_PINCM3, IOMUX_PINCM4,
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IOMUX_PINCM5, IOMUX_PINCM6,
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};
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#else
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#error "Series lookup table not supported"
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#endif /* if CONFIG_SOC_SERIES_MSPM0G */
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay) */
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#define GPIOB_NODE DT_NODELABEL(gpiob)
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#if DT_NODE_HAS_STATUS(GPIOB_NODE, okay)
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#ifdef CONFIG_SOC_SERIES_MSPM0G
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#define NUM_GPIOB_PIN 28
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#define gpiob_pins NUM_GPIOB_PIN
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static uint32_t gpiob_pincm_lut[NUM_GPIOB_PIN] = {
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IOMUX_PINCM12, IOMUX_PINCM13, IOMUX_PINCM15, IOMUX_PINCM16, IOMUX_PINCM17, IOMUX_PINCM18,
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IOMUX_PINCM23, IOMUX_PINCM24, IOMUX_PINCM25, IOMUX_PINCM26, IOMUX_PINCM27, IOMUX_PINCM28,
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IOMUX_PINCM29, IOMUX_PINCM30, IOMUX_PINCM31, IOMUX_PINCM32, IOMUX_PINCM33, IOMUX_PINCM43,
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IOMUX_PINCM44, IOMUX_PINCM45, IOMUX_PINCM48, IOMUX_PINCM49, IOMUX_PINCM50, IOMUX_PINCM51,
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IOMUX_PINCM52, IOMUX_PINCM56, IOMUX_PINCM57, IOMUX_PINCM58,
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};
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#endif /* CONFIG_SOC_SERIES_MSPM0G */
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay) */
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static int gpio_mspm0_port_get_raw(const struct device *port, uint32_t *value)
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{
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const struct gpio_mspm0_config *config = port->config;
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/* Read entire port */
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*value = DL_GPIO_readPins(config->base, UINT32_MAX);
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return 0;
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}
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static int gpio_mspm0_port_set_masked_raw(const struct device *port,
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uint32_t mask, uint32_t value)
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{
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const struct gpio_mspm0_config *config = port->config;
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DL_GPIO_writePinsVal(config->base, mask, value);
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return 0;
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}
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static int gpio_mspm0_port_set_bits_raw(const struct device *port,
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uint32_t mask)
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{
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const struct gpio_mspm0_config *config = port->config;
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DL_GPIO_setPins(config->base, mask);
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return 0;
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}
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static int gpio_mspm0_port_clear_bits_raw(const struct device *port,
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uint32_t mask)
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{
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const struct gpio_mspm0_config *config = port->config;
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DL_GPIO_clearPins(config->base, mask);
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return 0;
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}
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static int gpio_mspm0_port_toggle_bits(const struct device *port,
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uint32_t mask)
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{
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const struct gpio_mspm0_config *config = port->config;
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DL_GPIO_togglePins(config->base, mask);
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return 0;
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}
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static int gpio_mspm0_pin_configure(const struct device *port,
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gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_mspm0_config *config = port->config;
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/* determine pull up resistor value based on flags */
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DL_GPIO_RESISTOR pull_res;
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if (flags & GPIO_PULL_UP) {
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pull_res = DL_GPIO_RESISTOR_PULL_UP;
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} else if (flags & GPIO_PULL_DOWN) {
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pull_res = DL_GPIO_RESISTOR_PULL_DOWN;
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} else {
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pull_res = DL_GPIO_RESISTOR_NONE;
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}
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/* Config pin based on flags */
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switch (flags & (GPIO_INPUT | GPIO_OUTPUT)) {
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case GPIO_INPUT:
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DL_GPIO_initDigitalInputFeatures(config->pincm_lut[pin],
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DL_GPIO_INVERSION_DISABLE,
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pull_res,
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DL_GPIO_HYSTERESIS_DISABLE,
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DL_GPIO_WAKEUP_DISABLE);
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break;
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case GPIO_OUTPUT:
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DL_GPIO_initDigitalOutputFeatures(config->pincm_lut[pin],
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DL_GPIO_INVERSION_DISABLE,
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pull_res,
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DL_GPIO_DRIVE_STRENGTH_LOW,
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DL_GPIO_HIZ_DISABLE);
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/* Set initial state */
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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gpio_mspm0_port_set_bits_raw(port, BIT(pin));
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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gpio_mspm0_port_clear_bits_raw(port, BIT(pin));
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}
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/* Enable output */
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DL_GPIO_enableOutput(config->base, BIT(pin));
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break;
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case GPIO_DISCONNECTED:
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DL_GPIO_disableOutput(config->base, BIT(pin));
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int gpio_mspm0_pin_interrupt_configure(const struct device *port,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_mspm0_config *config = port->config;
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/* Config interrupt */
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switch (mode) {
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case GPIO_INT_MODE_DISABLED:
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DL_GPIO_clearInterruptStatus(config->base, BIT(pin));
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DL_GPIO_disableInterrupt(config->base, BIT(pin));
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break;
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case GPIO_INT_MODE_EDGE:
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uint32_t polarity = 0x00;
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if (trig & GPIO_INT_TRIG_LOW) {
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polarity |= BIT(0);
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}
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if (trig & GPIO_INT_TRIG_HIGH) {
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polarity |= BIT(1);
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}
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if (pin < MSPM0_PINS_LOW_GROUP) {
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DL_GPIO_setLowerPinsPolarity(config->base,
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polarity << (2 * pin));
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} else {
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DL_GPIO_setUpperPinsPolarity(config->base,
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polarity << (2 * (pin - MSPM0_PINS_LOW_GROUP)));
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}
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DL_GPIO_clearInterruptStatus(config->base, BIT(pin));
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DL_GPIO_enableInterrupt(config->base, BIT(pin));
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break;
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case GPIO_INT_MODE_LEVEL:
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return -ENOTSUP;
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}
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return 0;
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}
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static int gpio_mspm0_manage_callback(const struct device *port,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_mspm0_data *data = port->data;
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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static uint32_t gpio_mspm0_get_pending_int(const struct device *port)
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{
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const struct gpio_mspm0_config *config = port->config;
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return DL_GPIO_getPendingInterrupt(config->base);
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}
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static void gpio_mspm0_isr(const struct device *port)
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{
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struct gpio_mspm0_data *data;
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const struct gpio_mspm0_config *config;
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const struct device *dev_list[] = {
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DEVICE_DT_GET_OR_NULL(GPIOA_NODE),
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DEVICE_DT_GET_OR_NULL(GPIOB_NODE),
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};
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for (uint8_t i = 0; i < ARRAY_SIZE(dev_list); i++) {
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uint32_t status;
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if (dev_list[i] == NULL) {
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continue;
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}
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data = dev_list[i]->data;
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config = dev_list[i]->config;
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status = DL_GPIO_getRawInterruptStatus(config->base,
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0xFFFFFFFF);
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DL_GPIO_clearInterruptStatus(config->base, status);
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if (status != 0) {
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gpio_fire_callbacks(&data->callbacks,
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dev_list[i], status);
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}
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}
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}
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static int gpio_mspm0_init(const struct device *dev)
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{
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const struct gpio_mspm0_config *cfg = dev->config;
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static bool init_irq = true;
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/* Reset and enable GPIO banks */
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DL_GPIO_reset(cfg->base);
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DL_GPIO_enablePower(cfg->base);
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/* All the interrupt port share the same irq number, do it once */
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if (init_irq) {
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init_irq = false;
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IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
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gpio_mspm0_isr, DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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}
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return 0;
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}
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static const struct gpio_driver_api gpio_mspm0_driver_api = {
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.pin_configure = gpio_mspm0_pin_configure,
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.port_get_raw = gpio_mspm0_port_get_raw,
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.port_set_masked_raw = gpio_mspm0_port_set_masked_raw,
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.port_set_bits_raw = gpio_mspm0_port_set_bits_raw,
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.port_clear_bits_raw = gpio_mspm0_port_clear_bits_raw,
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.port_toggle_bits = gpio_mspm0_port_toggle_bits,
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.pin_interrupt_configure = gpio_mspm0_pin_interrupt_configure,
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.manage_callback = gpio_mspm0_manage_callback,
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.get_pending_int = gpio_mspm0_get_pending_int,
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};
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#define GPIO_DEVICE_INIT(n, __suffix, __base_addr) \
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static const struct gpio_mspm0_config gpio_mspm0_cfg_##__suffix = { \
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.common = { .port_pin_mask = \
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GPIO_PORT_PIN_MASK_FROM_NGPIOS(gpio##__suffix##_pins), \
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}, \
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.base = (GPIO_Regs *)__base_addr, \
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.pincm_lut = gpio##__suffix##_pincm_lut, \
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}; \
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static struct gpio_mspm0_data gpio_mspm0_data_##__suffix; \
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DEVICE_DT_DEFINE(n, gpio_mspm0_init, NULL, &gpio_mspm0_data_##__suffix, \
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&gpio_mspm0_cfg_##__suffix, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_mspm0_driver_api)
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#define GPIO_DEVICE_INIT_MSPM0(__suffix) \
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GPIO_DEVICE_INIT(DT_NODELABEL(gpio##__suffix), __suffix, \
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DT_REG_ADDR(DT_NODELABEL(gpio##__suffix)))
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay)
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GPIO_DEVICE_INIT_MSPM0(a);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay) */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay)
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GPIO_DEVICE_INIT_MSPM0(b);
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#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(gpiob), okay) */

‎dts/bindings/gpio/ti,mspm0-gpio.yaml

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# SPDX-License-Identifier: Apache-2.0
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description: TI MSPM0 GPIO
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compatible: "ti,mspm0-gpio"
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include: [gpio-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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"#gpio-cells":
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const: 2
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gpio-cells:
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- pin
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- flags

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