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| 1 | +/* |
| 2 | + * Copyright (c) 2025 Renesas Electronics Corporation |
| 3 | + * SPDX-License-Identifier: Apache-2.0 |
| 4 | + */ |
| 5 | + |
| 6 | +#include <zephyr/sw_isr_table.h> |
| 7 | +#include <zephyr/irq.h> |
| 8 | +#include <kswap.h> |
| 9 | +#include <zephyr/tracing/tracing.h> |
| 10 | +#include <zephyr/arch/rx/sw_nmi_table.h> |
| 11 | + |
| 12 | +#define NMI_NMIST_MASK 0x01 |
| 13 | +#define NMI_OSTST_MASK 0x02 |
| 14 | +#define NMI_IWDTST_MASK 0x08 |
| 15 | +#define NMI_LVD1ST_MASK 0x10 |
| 16 | +#define NMI_LVD2ST_MASK 0x20 |
| 17 | + |
| 18 | +#define NMIER_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), NMIER) |
| 19 | +#define NMISR_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), NMISR) |
| 20 | +#define NMICLR_BASE_ADDRESS DT_REG_ADDR_BY_NAME(DT_NODELABEL(icu), NMICLR) |
| 21 | +#define REG(addr) *((uint8_t *)(addr)) |
| 22 | + |
| 23 | +struct nmi_vector_entry _nmi_vector_table[NMI_TABLE_SIZE] = { |
| 24 | + {(nmi_callback_t)0xFFFFFFFFU, (void *)0xFFFFFFFFU}, /* NMI Pin Interrupt */ |
| 25 | + {(nmi_callback_t)0xFFFFFFFFU, |
| 26 | + (void *)0xFFFFFFFFU}, /* Oscillation Stop Detection Interrupt */ |
| 27 | + {(nmi_callback_t)0xFFFFFFFFU, (void *)0xFFFFFFFFU}, /* IWDT Underflow/Refresh Error */ |
| 28 | + {(nmi_callback_t)0xFFFFFFFFU, (void *)0xFFFFFFFFU}, /* Voltage Monitoring 1 Interrupt */ |
| 29 | + {(nmi_callback_t)0xFFFFFFFFU, (void *)0xFFFFFFFFU}, /* Voltage Monitoring 2 Interrupt */ |
| 30 | +}; |
| 31 | + |
| 32 | +void nmi_enable(uint8_t nmi_vector, nmi_callback_t callback, void *arg) |
| 33 | +{ |
| 34 | + if (nmi_vector >= NMI_TABLE_SIZE) { |
| 35 | + return; |
| 36 | + } |
| 37 | + |
| 38 | + _nmi_vector_table[nmi_vector].callback = callback; |
| 39 | + _nmi_vector_table[nmi_vector].arg = arg; |
| 40 | + |
| 41 | + switch (nmi_vector) { |
| 42 | + /* NMI Pin Interrupt */ |
| 43 | + case 0: |
| 44 | + REG(NMIER_BASE_ADDRESS) |= (1 << 0); |
| 45 | + break; |
| 46 | + /* Oscillation Stop Detection Interrupt */ |
| 47 | + case 1: |
| 48 | + REG(NMIER_BASE_ADDRESS) |= (1 << 1); |
| 49 | + break; |
| 50 | + /* IWDT Underflow/Refresh Error */ |
| 51 | + case 2: |
| 52 | + REG(NMIER_BASE_ADDRESS) |= (1 << 3); |
| 53 | + break; |
| 54 | + /* Voltage Monitoring 1 Interrupt */ |
| 55 | + case 3: |
| 56 | + REG(NMIER_BASE_ADDRESS) |= (1 << 4); |
| 57 | + break; |
| 58 | + /* Voltage Monitoring 2 Interrupt */ |
| 59 | + case 4: |
| 60 | + REG(NMIER_BASE_ADDRESS) |= (1 << 5); |
| 61 | + break; |
| 62 | + default: |
| 63 | + break; |
| 64 | + } |
| 65 | +} |
| 66 | + |
| 67 | +int get_nmi_request(void) |
| 68 | +{ |
| 69 | + uint8_t nmi_status = REG(NMISR_BASE_ADDRESS); |
| 70 | + |
| 71 | + if (nmi_status & NMI_NMIST_MASK) { |
| 72 | + return 0; |
| 73 | + } else if (nmi_status & NMI_OSTST_MASK) { |
| 74 | + return 1; |
| 75 | + } else if (nmi_status & NMI_IWDTST_MASK) { |
| 76 | + return 2; |
| 77 | + } else if (nmi_status & NMI_LVD1ST_MASK) { |
| 78 | + return 3; |
| 79 | + } else if (nmi_status & NMI_LVD2ST_MASK) { |
| 80 | + return 4; |
| 81 | + } |
| 82 | + |
| 83 | + return NMI_TABLE_SIZE; |
| 84 | +} |
| 85 | + |
| 86 | +void handle_nmi(uint8_t nmi_vector) |
| 87 | +{ |
| 88 | + if (nmi_vector >= NMI_TABLE_SIZE) { |
| 89 | + return; |
| 90 | + } |
| 91 | + |
| 92 | + _nmi_vector_table[nmi_vector].callback(_nmi_vector_table[nmi_vector].arg); |
| 93 | + |
| 94 | + switch (nmi_vector) { |
| 95 | + case 0: |
| 96 | + REG(NMICLR_BASE_ADDRESS) |= (1 << 0); |
| 97 | + break; |
| 98 | + case 1: |
| 99 | + REG(NMICLR_BASE_ADDRESS) |= (1 << 1); |
| 100 | + break; |
| 101 | + case 2: |
| 102 | + REG(NMICLR_BASE_ADDRESS) |= (1 << 3); |
| 103 | + break; |
| 104 | + case 3: |
| 105 | + REG(NMICLR_BASE_ADDRESS) |= (1 << 4); |
| 106 | + break; |
| 107 | + case 4: |
| 108 | + REG(NMICLR_BASE_ADDRESS) |= (1 << 5); |
| 109 | + break; |
| 110 | + default: |
| 111 | + break; |
| 112 | + } |
| 113 | +} |
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