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boards: beaglebone_ai64: Add BeagleBone AI-64
Add initial BeagleBone AI-64 support. BeagleBone AI-64: https://www.beagleboard.org/boards/beaglebone-ai-64 Signed-off-by: Prashanth S <[email protected]> Signed-off-by: Andrew Davis <[email protected]>
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‎boards/beagle/beaglebone_ai64/Kconfig.beaglebone_ai64‎

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# Copyright (C) 2023 BeagleBoard.org Foundation
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# Copyright (C) 2023 S Prashanth
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#
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_BEAGLEBONE_AI64
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select SOC_J721E_MAIN_R5F0_0 if BOARD_BEAGLEBONE_AI64_J721E_MAIN_R5F0_0

‎boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi‎

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/* Copyright (C) 2023 BeagleBoard.org Foundation
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* Copyright (C) 2023 S Prashanth
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* Copyright (c) 2024 Texas Instruments Incorporated
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* Andrew Davis <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
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&pinctrl {
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uart2_tx_default: uart2_tx_default {
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/* 0x1c is address of padconfig register of p8.34 and 14 is mux mode */
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pinmux = <K3_PINMUX(0x1c, PIN_OUTPUT, MUX_MODE_14)>;
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};
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uart2_rx_default: uart2_rx_default {
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/* 0x14 is address of padconfig register of p8.22 and 14 is mux mode */
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pinmux = <K3_PINMUX(0x14, PIN_INPUT, MUX_MODE_14)>;
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};
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};

‎boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts‎

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/* Copyright (C) 2023 BeagleBoard.org Foundation
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* Copyright (C) 2023 S Prashanth
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* Copyright (c) 2024 Texas Instruments Incorporated
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* Andrew Davis <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <ti/j721e_main_r5.dtsi>
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#include "beaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi"
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#include <freq.h>
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/ {
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model = "BeagleBoard.org BeagleBone AI-64";
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compatible = "beagle,beaglebone-ai64";
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chosen {
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zephyr,sram = &atcm;
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zephyr,console = &uart2;
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};
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cpus {
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cpu@0 {
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status = "okay";
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};
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};
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ddr0: memory@a2000000 {
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compatible = "mmio-sram";
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reg = <0xa2000000 DT_SIZE_M(1)>;
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};
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rsc_table: memory@a2100000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0xa2100000 DT_SIZE_M(1)>;
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zephyr,memory-region = "RSC_TABLE";
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};
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ddr1: memory@a2200000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0xa2200000 DT_SIZE_M(14)>;
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zephyr,memory-region = "DRAM";
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};
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};
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&uart2 {
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status = "okay";
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pinctrl-0 = <&uart2_tx_default &uart2_rx_default>;
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pinctrl-names = "default";
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current-speed = <115200>;
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};
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&systick_timer {
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status = "okay";
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};

‎boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.yaml‎

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# Copyright (C) 2023 BeagleBoard.org Foundation
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# Copyright (C) 2023 S Prashanth
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#
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# SPDX-License-Identifier: Apache-2.0
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identifier: beaglebone_ai64/j721e/main_r5f0_0
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name: BeagleBone-AI64 R5
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type: mcu
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arch: arm
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ram: 32
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toolchain:
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- zephyr
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- gnuarmemb
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- xtools
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supported:
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- uart
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vendor: beagle

‎boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0_defconfig‎

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# Copyright (C) 2023 BeagleBoard.org Foundation
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# Copyright (C) 2023 S Prashanth
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#
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# SPDX-License-Identifier: Apache-2.0
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# Zephyr Kernel Configuration
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CONFIG_XIP=n
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# Serial Driver
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CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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# Enable Console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y

‎boards/beagle/beaglebone_ai64/board.yml‎

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board:
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name: beaglebone_ai64
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vendor: beagle
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socs:
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- name: j721e

‎boards/beagle/beaglebone_ai64/doc/assets/bbai_64.webp‎

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‎boards/beagle/beaglebone_ai64/doc/index.rst‎

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.. _beaglebone_ai64:
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BeagleBone AI-64
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################
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Overview
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********
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BeagleBone AI-64 is a computational platform powered by TI J721E SoC, which is
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targeted for automotive applications.
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.. figure:: assets/bbai_64.webp
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:align: center
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:width: 600px
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:alt: BeagleBoard.org BeagleBone AI-64
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Hardware
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********
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BeagleBone AI-64 is powered by TI J721E SoC, which has three domains (MAIN,
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MCU, WKUP). This document gives overview of Zephyr running on Cortex R5's
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in the MAIN domain.
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L1 Memory System
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----------------
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* 16 KB instruction cache.
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* 16 KB data cache.
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* 64 KB TCM.
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Region Address Translation
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--------------------------
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The RAT module performs a region based address translation. It translates a
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32-bit input address into a 48-bit output address. Any input transaction that
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starts inside of a programmed region will have its address translated, if the
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region is enabled.
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VIM Interrupt Controller
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------------------------
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The VIM aggregates device interrupts and sends them to the R5F CPU(s). The VIM
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module supports 512 interrupt inputs per R5F core. Each interrupt can be either
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a level or a pulse (both active-high). The VIM has two interrupt outputs per core
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IRQ and FIQ.
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Supported Features
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******************
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The board configuration supports,
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+-----------+------------+-----------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=======================+
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| UART | on-chip | serial port-polling |
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| | | serial port-interrupt |
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+-----------+------------+-----------------------+
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Other hardwares features are currently not supported.
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Running Zephyr
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**************
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The J721E does not have a separate flash for the R5 cores. Because of this
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the A72 core has to load the program for the R5 cores to the right memory
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address, set the PC and start the processor.
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This can be done from Linux on the A72 core via remoteproc.
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By default the R5's Memory Protection Unit (MPU) only allows for execution of
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instructions in the ATCM/BTCM. There is also a couple regions of DRAM memory
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carved out for each R5 by Linux. These can be used for IPC (DDR0) and for
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data (DDR1). DDR1 can also be used for executable regions after programming
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the MPU.
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This is the memory mapping from A72 to the memory usable by the R5. Note that
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the R5 cores always see their local ATCM at address 0x00000000 and their BTCM
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at address 0x41010000. The ATCM/BTCM locations are fixed in hardware, but the
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DDR regions are by convention. If you would like to use different DRAM
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locations or sizes, you must also update for the same on the A72 software.
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(For Linux as the A72 host, this would be changed in Device Tree).
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+------------+--------------+--------------+--------------+--------------+--------+
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| Region | R5FSS0 Core0 | R5FSS0 Core1 | R5FSS1 Core0 | R5FSS1 Core1 | Size |
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+============+==============+==============+==============+==============+========+
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| ATCM | 0x05c00000 | 0x05d00000 | 0x05e00000 | 0x05f00000 | 32KB |
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+------------+--------------+--------------+--------------+--------------+--------+
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| BTCM | 0x05c10000 | 0x05d10000 | 0x05e10000 | 0x05f00000 | 32KB |
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+------------+--------------+--------------+--------------+--------------+--------+
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| DDR0 | 0xA2000000 | 0xA3000000 | 0xA4000000 | 0xA5000000 | 1MB |
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+------------+--------------+--------------+--------------+--------------+--------+
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| DDR1 | 0xA2100000 | 0xA3000000 | 0xA4100000 | 0xA5000000 | 15MB |
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+------------+--------------+--------------+--------------+--------------+--------+
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Steps to build and run an image
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-------------------------------
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Here is an example for the :zephyr:code-sample:`hello_world` application
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targeting one of the Cortex R5F on BeagleBone AI-64:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: beaglebone_ai64/j721e/main_r5f0_0
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:goals: build
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To load the image:
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| Copy Zephyr image to the /lib/firmware/ directory.
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| ``cp build/zephyr/zephyr.elf /lib/firmware/``
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|
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| Ensure the core is not running.
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| ``echo stop > /dev/remoteproc/j7-main-r5f0_0/state``
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|
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| Configuring the image name to the remoteproc module.
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| ``echo zephyr.elf > /dev/remoteproc/j7-main-r5f0_0/firmware``
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|
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| Once the image name is configured, send the start command.
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| ``echo start > /dev/remoteproc/j7-main-r5f0_0/state``
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Console
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-------
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Zephyr on BeagleBone AI-64 J721E Cortex R5 uses UART 2 (Rx p8.22, Tx p8.34)
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as console.
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References
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**********
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* `BeagleBone AI-64 Homepage <https://www.beagleboard.org/boards/beaglebone-ai-64>`_
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* `J721E TRM <https://www.ti.com/lit/zip/spruil1>`_

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