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Tavish Naruka
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drivers: intc: add vim_tms570 interrupt controller
Add TI VIM driver specific to the TMS570 chips. This driver/peripheral is not compatible with the existing intc_vim.c for some other TI chips. Signed-off-by: Tavish Naruka <[email protected]>
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‎drivers/interrupt_controller/CMakeLists.txt‎

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@@ -33,6 +33,7 @@ zephyr_library_sources_ifdef(CONFIG_INTC_ESP32 intc_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_SWERV_PIC intc_swerv_pic.c)
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zephyr_library_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ intc_vexriscv_litex.c)
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zephyr_library_sources_ifdef(CONFIG_VIM intc_vim.c)
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zephyr_library_sources_ifdef(CONFIG_TMS570_VIM intc_tms570_vim.c)
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zephyr_library_sources_ifdef(CONFIG_CLIC intc_clic.c)
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zephyr_library_sources_ifdef(CONFIG_CLIC intc_clic.S)
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zephyr_library_sources_ifdef(CONFIG_NRFX_CLIC intc_nrfx_clic.c)

‎drivers/interrupt_controller/Kconfig‎

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@@ -102,6 +102,8 @@ source "drivers/interrupt_controller/Kconfig.nxp_pint"
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source "drivers/interrupt_controller/Kconfig.vim"
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source "drivers/interrupt_controller/Kconfig.tms570_vim"
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source "drivers/interrupt_controller/Kconfig.renesas_rz"
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source "drivers/interrupt_controller/Kconfig.nxp_irqsteer"

‎drivers/interrupt_controller/Kconfig.tms570_vim‎

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# Copyright (C) 2025 ispace, inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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config TMS570_VIM
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bool "TI Vectored Interrupt Manager (TMS570)"
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default y
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depends on DT_HAS_TI_TMS570_VIM_ENABLED
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help
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The TI Vectored Interrupt Manager provides hardware assistance for prioritizing
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and aggregating the interrupt sources for TI herules ARM Cortex-R4/R5 processor cores.

‎drivers/interrupt_controller/intc_tms570_vim.c‎

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/*
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* Copyright (C) 2025 ispace, inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/irq.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/sys/printk.h>
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#include <zephyr/sys/reboot.h>
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#include "soc_internal.h"
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#include <string.h>
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#define DT_DRV_COMPAT ti_tms570_vim
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#define DRV_CONTROL_REG DT_INST_REG_ADDR_BY_IDX(0, 0)
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#define DRV_ECC_REG DT_INST_REG_ADDR_BY_IDX(0, 1)
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#define DRV_VIMRAM_REG DT_INST_REG_ADDR_BY_IDX(0, 2)
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#define DRV_VIMRAM_REG_SIZE DT_INST_REG_SIZE_BY_IDX(0, 2)
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/* control registers */
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#define VIM_REG_IRQINDEX (DRV_CONTROL_REG + 0x00)
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#define VIM_REG_FIQINDEX (DRV_CONTROL_REG + 0x04)
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#define VIM_REG_REQMASKSET_0 (DRV_CONTROL_REG + 0x30)
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#define VIM_REG_REQMASKCLR_0 (DRV_CONTROL_REG + 0x40)
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/* ECC related registers */
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#define VIM_ECC_CTL (DRV_ECC_REG + 0xF0)
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#define REQUMASK_IRQ_PER_REG (32u)
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static inline void set_reqmask_bit(unsigned int irq, uintptr_t reg_0_addr)
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{
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sys_write32(1 << (irq % REQUMASK_IRQ_PER_REG),
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reg_0_addr + (irq / REQUMASK_IRQ_PER_REG) * sizeof(uint32_t));
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}
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static inline int get_reqmask_bit(unsigned int irq, uintptr_t reg_0_addr)
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{
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return sys_read32(reg_0_addr + (irq / REQUMASK_IRQ_PER_REG) * sizeof(uint32_t));
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}
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/* count of number of times the phantom interrupt happened */
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unsigned int nr_phantom_isr;
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static void phantom_isr(void)
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{
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/**
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* we don't want this to call the z_spurious_irq because we have seen
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* phantom irq happen even though we don't expect it to happen.
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*/
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nr_phantom_isr++;
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}
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#if defined(CONFIG_RUNTIME_NMI)
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static void tms570_nmi_handler(void)
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{
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uint32_t vec = sys_read32(REG_ESM_IOFFHR) - 1;
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if (vec < 32) {
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sys_write32(1 << vec, REG_ESM_SR1_0);
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printk("\nESM Group 1 chan %u\n", vec);
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} else if (vec < 64) {
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sys_write32(1 << (vec - 32), REG_ESM_SR1_1);
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printk("\nESM Group 2 chan %u\n", vec - 32);
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} else if (vec < 96U) {
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sys_write32(1 << (vec - 64), REG_ESM_SR4_0);
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printk("\nESM Group 1 chan %u\n", vec - 32);
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} else if ((vec >= 128U) && (vec < 160U)) {
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sys_write32(1 << (vec - 128), REG_ESM_SR7_0);
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printk("\nESM Group 1 chan %u\n", vec - 96);
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} else {
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sys_write32(0xFFFFFFFF, REG_ESM_SR7_0);
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sys_write32(0xFFFFFFFF, REG_ESM_SR4_0);
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sys_write32(0xFFFFFFFF, REG_ESM_SR1_0);
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sys_write32(0xFFFFFFFF, REG_ESM_SR1_1);
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}
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sys_reboot(SYS_REBOOT_WARM);
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}
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#endif
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/**
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* @brief Get active interrupt ID (IRQ only)
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*
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* @return Returns the ID of an active interrupt
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*/
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unsigned int z_soc_irq_get_active(void)
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{
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unsigned int irq_idx;
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/* a 0 means phantom ISR, channel 0 starts from index 1 */
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irq_idx = sys_read32(VIM_REG_IRQINDEX);
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if (irq_idx > 0) {
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z_soc_irq_disable(irq_idx - 1);
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return irq_idx - 1;
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} else {
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phantom_isr();
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}
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return (CONFIG_NUM_IRQS + 1);
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}
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void z_soc_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
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{
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/**
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* not supported, all IRQ sources generate IRQ, instead of FIQ,
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* and with the default priority.
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*/
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}
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void z_soc_irq_enable(unsigned int irq)
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{
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set_reqmask_bit(irq, VIM_REG_REQMASKSET_0);
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}
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void z_soc_irq_disable(unsigned int irq)
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{
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set_reqmask_bit(irq, VIM_REG_REQMASKCLR_0);
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}
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int z_soc_irq_is_enabled(unsigned int irq)
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{
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return get_reqmask_bit(irq, VIM_REG_REQMASKSET_0);
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}
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/**
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* @brief Signal end-of-interrupt
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*
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* @param irq interrupt ID
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*/
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void z_soc_irq_eoi(unsigned int irq)
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{
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z_soc_irq_enable(irq);
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}
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void z_soc_irq_init(void)
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{
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/**
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* ref. SPNA218.pdf
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* We are implementing what is referred to as "Legacy ARM7 Interrupts".
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* We do not use the VIM_RAM at all.
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* Sequence is like this:
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* 1. Interrupt request happens
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* 2. Exception vector 0x18 (IRQ) or 0x1C (FIQ) is taken
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* - in case of IRQ "ldr pc, =_isr_wrapper"
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* - in case of FIQ "ldr pc, =z_arm_nmi"
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* 3. _isr_wrapper uses z_soc_irq_get_active to get index into
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* _sw_isr_table for arg and ISR handler
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* 4. run ISR handler
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*
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* Drivers attach interrupts using IRQ_CONNECT/IRQ_DIRECT_CONNECT like:
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* IRQ_CONNECT(irqnum, irqnum, z_irq_spurious, NULL, 0);
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*/
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/* Errata VIM#28 Workaround: Disable Single Bit error correction */
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sys_write32((0xAU << 0U) | (0x5U << 16U), VIM_ECC_CTL);
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/**
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* We do not use VIM RAM, or need to care about ECC, but if we do not set
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* the VIM RAM locations to a _valid_ memory address (memset to 0 doesn't work),
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* it keeps generating ESM NMI with ESM group 1 status = 0x80008000.
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* Doing the following stops it.
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*/
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uint32_t *p = (void *) DRV_VIMRAM_REG;
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for (int i = 0; i < DRV_VIMRAM_REG_SIZE / 4; i++) {
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*(p + i) = (uint32_t) &z_irq_spurious;
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}
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#if defined(CONFIG_RUNTIME_NMI)
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z_arm_nmi_set_handler(tms570_nmi_handler);
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#endif
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/* enable interrupt */
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arch_irq_unlock(0);
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}

‎dts/arm/ti/tms570.dtsi‎

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status = "okay";
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};
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vim: interrupt-controller@fffffe00 {
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compatible = "ti,tms570-vim";
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reg = <0xfffffe00 0x00000100>, /* VIM control */
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<0xfffffd00 0x00000100>, /* ECC related */
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<0xfff82000 128>; /* VIM_RAM */
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status = "okay";
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interrupt-controller;
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#interrupt-cells = <2>;
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#address-cells = <1>;
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};
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sci1: uart@fff7e400 {
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compatible = "ti,tms570-uart";
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reg = <0xfff7e400 256>;

‎dts/bindings/interrupt-controller/ti,tms570-vim.yaml‎

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# Copyright (c) 2025 ispace, inc.
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# SPDX-License-Identifier: Apache-2.0
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description: VIM for TMS570
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compatible: "ti,tms570-vim"
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include: [interrupt-controller.yaml, base.yaml]
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properties:
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# NOTE: Register ranges:
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# - 0 : VIM control registers
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# - 1 : VIM ECC related registers
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# - 2 : VIM RAM
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reg:
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required: true
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"#interrupt-cells":
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const: 2
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interrupt-cells:
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- irq
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- priority

‎soc/ti/hercules/ti_tms570lc43x/Kconfig.defconfig‎

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if SOC_TI_TMS570LC43X
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config SYS_CLOCK_EXISTS
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default n
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default y
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config MULTITHREADING
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default y
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config DYNAMIC_INTERRUPTS
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default n
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config GEN_SW_ISR_TABLE
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default n
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default y
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config GEN_ISR_TABLES
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default y
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config GEN_IRQ_VECTOR_TABLE
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default n
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# launchpad is 16MHz
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config USE_SWITCH
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default n
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config RUNTIME_NMI
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default y
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# 10ms OS tick from a 1MHz free-running clock
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config SYS_CLOCK_TICKS_PER_SEC
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default 100
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/soc/rti,clock-frequency)
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