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boards: nxp: add frdm_mcxe31b board support
- support XIP way to boot - add board doc and picture - enable cases below: hello_world/blinky/button/ philosophers/synchronization/ gpio_basic_api Signed-off-by: Lucien Zhao <[email protected]>
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‎boards/nxp/frdm_mcxe31b/CMakeLists.txt‎

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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if(CONFIG_BOARD_NXP_MCXE31X_BOOT_HEADER)
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zephyr_library_sources(boot_header/boot_header.c)
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zephyr_library_include_directories(boot_header)
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endif()

‎boards/nxp/frdm_mcxe31b/Kconfig‎

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_NXP_MCXE31X_BOOT_HEADER
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bool "MCXE31x boot header support"
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select SOC_NXP_MCXE31X_BOOT_HEADER
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default y
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help
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Enable this option to include the MCXE31x boot header in the final
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image. The boot header is required for proper operation of the
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on-chip bootloader.
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See the MCXE31x reference manual for more details.

‎boards/nxp/frdm_mcxe31b/Kconfig.frdm_mcxe31b‎

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_FRDM_MCXE31B
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select SOC_PART_NUMBER_MCXE31BMPB

‎boards/nxp/frdm_mcxe31b/board.cmake‎

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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board_runner_args(jlink "--device=MCXE31B")
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board_runner_args(linkserver "--device=MCXE31B:FRDM-MCXE31B")
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include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

‎boards/nxp/frdm_mcxe31b/board.yml‎

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board:
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name: frdm_mcxe31b
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full_name: FRDM-MCXE31B
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vendor: nxp
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socs:
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- name: mcxe31b

‎boards/nxp/frdm_mcxe31b/boot_header/boot_header.c‎

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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "boot_header.h"
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#include "fsl_common.h"
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/******************************************************************************
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* External references
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******************************************************************************/
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#if defined(CONFIG_BOARD_NXP_MCXE31X_BOOT_HEADER) && (CONFIG_BOARD_NXP_MCXE31X_BOOT_HEADER != 0U)
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extern void *const _vector_start;
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/******************************************************************************
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* Boot Header
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******************************************************************************/
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typedef struct image_vector_table {
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uint32_t header; /* header */
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uint32_t boot_config; /* Boot configuration Word */
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const uint32_t reserved1; /* Reserved */
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const uint32_t *cm7_0_start_address; /* Start address of CM7_0 Core */
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const uint32_t reserved2; /* Reserved */
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const uint32_t *reserved3; /* Reserved */
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const uint32_t reserved4; /* Reserved */
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const uint32_t *reserved5; /* Reserved */
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const uint32_t *reserved6; /* Reserved */
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const uint32_t *lcc_config; /* Address of LC config */
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uint8_t reserved7[216]; /* Reserved for future use */
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} ivt_t;
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/******************************************************************************
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* SBAF definitions
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******************************************************************************/
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/* CM7_0_ENABLE: */
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/* 0- Cortex-M7_0 application core clock gated after boot */
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/* 1- Cortex-M7_0 application core clock un-gated after boot */
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#define CM7_0_ENABLE_MASK 1U
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/* Control the boot flow of the application: */
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/* 0- Non-Secure Boot- Application image is started by SBAF without any */
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/* authentication in parallel to HSE firmware. */
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/* 1- Secure Boot- Application image is executed by HSE firmware after the */
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/* authentication. SBAF only starts the HSE firmware after successful */
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/* authentication. */
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#define BOOT_SEQ_MASK 8U
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/* APP_SWT_INIT: Control SWT0 before starting application core(s): */
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/* 0- Disable. */
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/* 1- Enable. SBAF initializes SWT0 before enabling application cores. */
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/* SBAF scans this bit only when BOOT_SEQ bit is 0. */
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#define APP_SWT_INIT_MASK 32U
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/*!
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* @brief Sets register field in peripheral configuration structure.
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* @details This macro sets register field <c>mask</c> in the peripheral
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* configuration structure.
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* @param mask Register field to be set.
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* @note Implemented as a macro.
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*/
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#define SET(mask) (mask)
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/*!
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* @brief Clears register field in peripheral configuration structure.
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* @details This macro clears register field <c>mask</c> in the peripheral
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* configuration structure.
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* @param mask Register field to be cleared.
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* @note Implemented as a macro.
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*/
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#define CLR(mask) 0
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const ivt_t _boot_header __attribute__((used, section(".boot_header"))) = {
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.header = 0x5AA55AA5,
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.boot_config = SET(CM7_0_ENABLE_MASK) | /* booting core is core0 */
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CLR(BOOT_SEQ_MASK) | /* unsecure boot is only supported */
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CLR(APP_SWT_INIT_MASK), /* SWT0 is not setup by BAF */
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.cm7_0_start_address = (const uint32_t *)&_vector_start,
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.lcc_config = (const uint32_t *)&lc_config};
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/******************************************************************************
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* Default configurations that can be overridden by strong definitions
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******************************************************************************/
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__WEAK const boot_lc_config_t lc_config = 0xffffffff;
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#endif /* CONFIG_BOARD_NXP_MCXE31X_BOOT_HEADER */
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/******************************************************************************
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* End of module
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******************************************************************************/

‎boards/nxp/frdm_mcxe31b/boot_header/boot_header.h‎

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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_BOOT_HEADER_H_
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#define ZEPHYR_INCLUDE_BOOT_HEADER_H_
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#include "fsl_common.h"
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/******************************************************************************
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* Configuration structure definition *
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******************************************************************************/
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typedef uint32_t boot_lc_config_t;
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extern const boot_lc_config_t lc_config;
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#endif /* ZEPHYR_INCLUDE_BOOT_HEADER_H_ */

‎boards/nxp/frdm_mcxe31b/doc/frdm_mcxe31b.webp‎

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‎boards/nxp/frdm_mcxe31b/doc/index.rst‎

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.. zephyr:board:: frdm_mcxe31b
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Overview
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********
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The FRDM-MCXE31B board is a design and evaluation platform based on the NXP MCXE31B
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microcontroller (MCU). NXP MCXE31B MCU based on an Arm Cortex-M7 core, running at
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speeds of up to 160 MHz with a 2.97 to 5.5V supply.
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Hardware
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********
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- MCXE31B Arm Cortex-M7 microcontroller running up to 160 MHz
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- 4MB dual-bank on chip Flash
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- 320KB SRAM + 192KB TCM
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- 2x I2C
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- 6x SPI
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- 16x UART
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- On-board MCU-Link debugger with CMSIS-DAP
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- Arduino Header, mikroBUS
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For more information about the MCXE31B SoC and FRDM-MCXE31B board, see:
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- `MCXE31X Datasheet`_
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- `MCXE31X Reference Manual`_
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- `FRDM-MCXE31B Board User Manual`_
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Connections and IOs
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===================
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Each GPIO port is divided into two banks: low bank, from pin 0 to 15, and high
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bank, from pin 16 to 31. For example, ``PTA2`` is the pin 2 of ``gpioa_l`` (low
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bank), and ``PTA20`` is the pin 4 of ``gpioa_h`` (high bank).
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The GPIO controller provides the option to route external input pad interrupts
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to either the SIUL2 EIRQ or WKPU interrupt controllers, as supported by the SoC.
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By default, GPIO interrupts are routed to SIUL2 EIRQ interrupt controller,
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unless they are explicity configured to be directed to the WKPU interrupt
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controller, as outlined in :zephyr_file:`dts/bindings/gpio/nxp,siul2-gpio.yaml`.
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To find information about which GPIOs are compatible with each interrupt
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controller, refer to the device reference manual.
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+-------+-------------+---------------------------+
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| Name | Function | Usage |
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+=======+=============+===========================+
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| PTC16 | GPIO | Red LED |
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+-------+-------------+---------------------------+
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| PTB22 | GPIO | Green LED |
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+-------+-------------+---------------------------+
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| PTC14 | GPIO | Blue LED |
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+-------+-------------+---------------------------+
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| PTE3 | LPUART5_RX | UART Console |
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+-------+-------------+---------------------------+
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| PTE14 | LPUART5_TX | UART Console |
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+-------+-------------+---------------------------+
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System Clock
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============
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The MCXE31B SoC is configured to use PLL running at 160MHz as a source for
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the system clock.
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Serial Port
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===========
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The MCXE31B LPUART5 is used for the console.
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Programming and Debugging
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*************************
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.. zephyr:board-supported-runners::
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Build and flash applications as usual (see :ref:`build_an_application` and
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:ref:`application_run` for more details).
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Configuring a Debug Probe
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=========================
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A debug probe is used for both flashing and debugging the board. This board is
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configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
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Using LinkServer
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----------------
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Linkserver is the default runner for this board, and supports the factory
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default MCU-Link firmware. Follow the instructions in
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:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
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firmware. This only needs to be done if the default onboard debug circuit
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firmware was changed. To put the board in ``ISP mode`` to program the firmware,
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short jumper JP3.
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Using J-Link
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------------
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There are two options. The onboard debug circuit can be updated with Segger
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J-Link firmware by following the instructions in
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:ref:`mcu-link-jlink-onboard-debug-probe`.
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To be able to program the firmware, you need to put the board in ``ISP mode``
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by shorting the jumper JP3.
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The second option is to attach a :ref:`jlink-external-debug-probe` to the
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10-pin SWD connector (J14) of the board.
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For both options use the ``-r jlink`` option with west to use the jlink runner.
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.. code-block:: console
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west flash -r jlink
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Configuring a Console
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=====================
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Connect a USB cable from your PC to J13, and use the serial terminal of your choice
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(minicom, putty, etc.) with the following settings:
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- Speed: 115200
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- Data: 8 bits
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- Parity: None
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- Stop bits: 1
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Flashing
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========
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Here is an example for the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: frdm_mcxe31b
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:goals: flash
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Open a serial terminal, reset the board (press the RESET button), and you should
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see the following message in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build v4.2.0-2092-g17e93a718422 ***
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Hello World! frdm_mcxe31b/mcxe31b
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Debugging
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=========
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Here is an example for the :zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: frdm_mcxe31b
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:goals: debug
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Open a serial terminal, step through the application in your debugger, and you
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should see the following message in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build v4.2.0-2092-g17e93a718422 ***
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Hello World! frdm_mcxe31b/mcxe31b
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Troubleshooting
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===============
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.. include:: ../../common/segger-ecc-systemview.rst.inc
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.. include:: ../../common/board-footer.rst.inc
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.. _MCXE31X Datasheet:
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https://www.nxp.com/docs/en/data-sheet/MCXEP172M160FB0.pdf
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.. _MCXE31X Reference Manual:
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https://www.nxp.com/webapp/Download?colCode=MCXE31XRM&location=null
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.. _FRDM-MCXE31B Board User Manual:
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https://www.nxp.com/webapp/Download?colCode=UM12330&location=null&isHTMLorPDF=HTML

‎boards/nxp/frdm_mcxe31b/frdm_mcxe31b-pinctrl.dtsi‎

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/*
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* Copyright 2025 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/mcx/MCXE31BMPB-pinctrl.h>
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&pinctrl {
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eirq0_default: eirq0_default {
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group1 {
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pinmux = <PTD5_EIRQ13>;
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input-enable;
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};
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};
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pinmux_lpuart_5: pinmux_lpuart_5 {
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group1 {
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pinmux = <PTE14_LPUART5_TX_O>;
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output-enable;
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};
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group2 {
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pinmux = <PTE3_LPUART5_RX>;
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input-enable;
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};
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};
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};

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