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24 | 24 | .CONF_HYS0 = TI_TMP108_CONF_NA,\
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25 | 25 | .CONF_CR0 = 0x0040, \
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26 | 26 | .CONF_CR1 = 0x0080, \
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| 27 | + .CONF_SLEEP = 0x0100, \ |
27 | 28 | .CONF_M1 = 0x0000, \
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28 | 29 | .CONF_TM = 0x0200, \
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29 | 30 | .CONF_POL = 0x0400, \
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47 | 48 | .WAKEUP_TIME_IN_MS = 30 }
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48 | 49 |
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49 | 50 | #define TI_TMP108_MODE_SHUTDOWN(x) 0
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50 |
| -#define TI_TMP108_MODE_ONE_SHOT(x) TI_TMP108_CONF_M0(x) |
| 51 | +#define TI_TMP108_MODE_ONE_SHOT(x) (TI_TMP108_CONF_M0(x) | TI_TMP108_CONF_SLEEP(x)) |
51 | 52 | #define TI_TMP108_MODE_CONTINUOUS(x) TI_TMP108_CONF_M1(x)
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52 |
| -#define TI_TMP108_MODE_MASK(x) ~(TI_TMP108_CONF_M0(x) | TI_TMP108_CONF_M1(x)) |
| 53 | +#define TI_TMP108_MODE_MASK(x) ~(TI_TMP108_CONF_M0(x) | \ |
| 54 | + TI_TMP108_CONF_M1(x) | \ |
| 55 | + TI_TMP108_CONF_SLEEP(x)) |
53 | 56 |
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54 | 57 | #define TI_TMP108_FREQ_4_SECS(x) 0
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55 | 58 | #define TI_TMP108_FREQ_1_HZ(x) TI_TMP108_GET_CONF(x, CONF_CR0)
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77 | 80 |
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78 | 81 | #define TI_TMP108_CONF_M1(x) TI_TMP108_GET_CONF(x, CONF_M1)
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79 | 82 | #define TI_TMP108_CONF_M0(x) TI_TMP108_GET_CONF(x, CONF_M0)
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| 83 | +#define TI_TMP108_CONF_SLEEP(x) TI_TMP108_GET_CONF(x, CONF_SLEEP) |
80 | 84 |
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81 | 85 | #define TMP108_TEMP_MULTIPLIER(x) TI_TMP108_GET_CONF(x, TEMP_MULT)
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82 | 86 | #define TMP108_TEMP_DIVISOR(x) TI_TMP108_GET_CONF(x, TEMP_DIV)
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88 | 92 | struct tmp_108_reg_def {
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89 | 93 | uint16_t CONF_M0; /** Mode 1 configuration bit */
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90 | 94 | uint16_t CONF_M1; /** Mode 2 configuration bit */
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| 95 | + uint16_t CONF_SLEEP; /** Sleep mode configuration bit */ |
91 | 96 | uint16_t CONF_CR0; /** Conversion rate 1 configuration bit */
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92 | 97 | uint16_t CONF_CR1; /** Conversion rate 2 configuration bit */
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93 | 98 | uint16_t CONF_POL; /** Alert pin Polarity configuration bit */
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