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soc: st: stm32u3: Add STM32U3C5 SoC entry #105473
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filipembedded
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,23 @@ | ||
| /* | ||
| * Copyright (c) 2026 Filip Stojanovic <filipembedded@gmail.com> | ||
| * | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| */ | ||
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| #include <st/u3/stm32u3.dtsi> | ||
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| / { | ||
| soc { | ||
| compatible = "st,stm32u3c5", "st,stm32u3", "simple-bus"; | ||
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| pinctrl: pin-controller@42020000 { | ||
| gpiof: gpio@42021400 { | ||
| compatible = "st,stm32-gpio"; | ||
| gpio-controller; | ||
| #gpio-cells = <2>; | ||
| reg = <0x42021400 0x400>; | ||
| clocks = <&rcc STM32_CLOCK(AHB2, 5)>; | ||
| }; | ||
| }; | ||
| }; | ||
| }; | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,26 @@ | ||
| /* | ||
| * Copyright (c) 2026 Filip Stojanovic <filipembedded@gmail.com> | ||
| * | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| */ | ||
|
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| #include <st/u3/stm32u3c5.dtsi> | ||
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| / { | ||
| sram0: memory@20000000 { | ||
| compatible = "zephyr,memory-region", "mmio-sram"; | ||
| reg = <0x20000000 DT_SIZE_K(640)>; | ||
| zephyr,memory-region = "SRAM0"; | ||
| }; | ||
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| soc { | ||
| flash-controller@40022000 { | ||
| flash0: flash@8000000 { | ||
| reg = <0x08000000 DT_SIZE_K(2048)>; | ||
| ranges = <0x0 0x08000000 DT_SIZE_K(2048)>; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| }; | ||
| }; | ||
| }; | ||
| }; |
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Please do it as follows (ie move under soc node).
This is the same in the end, but preferred for consistency
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I understand. Done