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Merged
merged 15 commits into from
Jan 11, 2021
Merged

cAVS updates #31127

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cc5fa5b
rimage: update rimage: add configuration and extended manifest
lyakh Oct 27, 2020
8bc8fb4
cavs: fix manifest base address
lyakh Oct 7, 2020
f22452e
sof: remove superfluous and duplicate code
lyakh Nov 3, 2020
9019b29
cavs: disable all interrupts when configuring interrupt controllers
lyakh Oct 7, 2020
e56c0b6
xtensa: disable unused memory power down
lyakh Oct 7, 2020
2cd51ac
cavs: fix shim register location on 1.8 and above
lyakh Oct 7, 2020
8826f18
xtensa: IPM is only required if SMP is enabled
lyakh Oct 7, 2020
70059f4
cavs: (cosmetic) clean up and simplification of intc_cavs.c
lyakh Oct 7, 2020
93975ef
cavs_v18, v20, v25: calculate trace base address correctly
lyakh Jan 4, 2021
d7c9e40
cavs_v25: switch over to Tigerlake H configuration
lyakh Jan 4, 2021
d4a0ea4
cavs_v25: fix copy-pasted definitions
lyakh Jan 4, 2021
84b4c93
cavs: remove unused mcuboot support
lyakh Jan 4, 2021
61bf1b2
cavs: fix LSPGISTS and LSPGCTL access
lyakh Jan 4, 2021
a53b228
cavs: (cosmetic) remove redundant LPRAM_* macros
lyakh Jan 5, 2021
a518366
bootloader: use ceiling_fraction() instead of open-coding it
lyakh Jan 5, 2021
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18 changes: 16 additions & 2 deletions scripts/west_commands/sign.py
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Original file line number Diff line number Diff line change
Expand Up @@ -420,19 +420,33 @@ def sign(self, command, build_dir, bcfg, formats):
board = cache['CACHED_BOARD']
log.inf('Signing for board ' + board)
target = self.edt_get_rimage_target(board)
log.inf('Signing for SOC target ' + target)
conf = target + '.toml'
log.inf('Signing for SOC target ' + target + ' using ' + conf)

if not args.quiet:
log.inf('Signing with tool {}'.format(tool_path))

bootloader = str(b / 'zephyr' / 'bootloader.elf.mod')
kernel = str(b / 'zephyr' / 'zephyr.elf.mod')
out_bin = str(b / 'zephyr' / 'zephyr.ri')
out_xman = str(b / 'zephyr' / 'zephyr.ri.xman')
out_tmp = str(b / 'zephyr' / 'zephyr.rix')
rimage_conf = pathlib.Path(cache['RIMAGE_CONFIG_PATH'])
conf_path = str(rimage_conf / conf)

sign_base = ([tool_path] + args.tool_args +
['-o', out_bin, '-m', target, '-i', '3'] +
['-o', out_bin, '-c', conf_path, '-i', '3', '-e'] +
[bootloader, kernel])

if not args.quiet:
log.inf(quote_sh_list(sign_base))
subprocess.check_call(sign_base)

filenames = [out_xman, out_bin]
with open(out_tmp, 'wb') as outfile:
for fname in filenames:
with open(fname, 'rb') as infile:
outfile.write(infile.read())

os.remove(out_bin)
os.rename(out_tmp, out_bin)
2 changes: 2 additions & 0 deletions soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
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Original file line number Diff line number Diff line change
Expand Up @@ -142,6 +142,8 @@
#define LOG_ENTRY_ELF_BASE 0x20000000
#define LOG_ENTRY_ELF_SIZE 0x2000000

#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
#define EXT_MANIFEST_ELF_SIZE 0x2000000

#define SRAM_ALIAS_BASE 0x9E000000
#define SRAM_ALIAS_MASK 0xFF000000
Expand Down
15 changes: 15 additions & 0 deletions soc/xtensa/intel_adsp/cavs_v15/linker.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -132,6 +132,9 @@ MEMORY
static_log_entries_seg (!ari) :
org = LOG_ENTRY_ELF_BASE,
len = LOG_ENTRY_ELF_SIZE
fw_metadata_seg (!ari) :
org = EXT_MANIFEST_ELF_BASE,
len = EXT_MANIFEST_ELF_SIZE
}

PHDRS
Expand Down Expand Up @@ -161,6 +164,7 @@ PHDRS
ucram_phdr PT_LOAD;
static_uuid_entries_phdr PT_NOTE;
static_log_entries_phdr PT_NOTE;
metadata_entries_phdr PT_NOTE;
}
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
Expand Down Expand Up @@ -205,6 +209,11 @@ _memmap_cacheattr_bp_allvalid = 0x22222222;
_memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;

PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);

_EXT_MAN_ALIGN_ = 16;
EXTERN(ext_man_fw_ver)
EXTERN(ext_man_cavs_config)

SECTIONS
{

Expand Down Expand Up @@ -567,4 +576,10 @@ SECTIONS
{
*(*.static_log*)
} > static_log_entries_seg :static_log_entries_phdr

.fw_metadata (COPY) : ALIGN(1024)
{
KEEP (*(.fw_metadata))
. = ALIGN(_EXT_MAN_ALIGN_);
} >fw_metadata_seg :metadata_entries_phdr
}
2 changes: 2 additions & 0 deletions soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
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Original file line number Diff line number Diff line change
Expand Up @@ -139,6 +139,8 @@
#define LOG_ENTRY_ELF_BASE 0x20000000
#define LOG_ENTRY_ELF_SIZE 0x2000000

#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
#define EXT_MANIFEST_ELF_SIZE 0x2000000

#define SRAM_ALIAS_BASE 0x9E000000
#define SRAM_ALIAS_MASK 0xFF000000
Expand Down
15 changes: 15 additions & 0 deletions soc/xtensa/intel_adsp/cavs_v18/linker.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -112,6 +112,9 @@ MEMORY
static_log_entries_seg (!ari) :
org = LOG_ENTRY_ELF_BASE,
len = LOG_ENTRY_ELF_SIZE
fw_metadata_seg (!ari) :
org = EXT_MANIFEST_ELF_BASE,
len = EXT_MANIFEST_ELF_SIZE
}

PHDRS
Expand Down Expand Up @@ -141,6 +144,7 @@ PHDRS

static_uuid_entries_phdr PT_NOTE;
static_log_entries_phdr PT_NOTE;
metadata_entries_phdr PT_NOTE;
}
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
Expand Down Expand Up @@ -194,6 +198,11 @@ _memmap_cacheattr_intel_cavs18_adsp = 0xFF22FFF2;
#endif

PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs18_adsp);

_EXT_MAN_ALIGN_ = 16;
EXTERN(ext_man_fw_ver)
EXTERN(ext_man_cavs_config)

SECTIONS
{

Expand Down Expand Up @@ -532,4 +541,10 @@ SECTIONS
{
*(*.static_log*)
} > static_log_entries_seg :static_log_entries_phdr

.fw_metadata (COPY) : ALIGN(1024)
{
KEEP (*(.fw_metadata))
. = ALIGN(_EXT_MAN_ALIGN_);
} >fw_metadata_seg :metadata_entries_phdr
}
2 changes: 2 additions & 0 deletions soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
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Original file line number Diff line number Diff line change
Expand Up @@ -139,6 +139,8 @@
#define LOG_ENTRY_ELF_BASE 0x20000000
#define LOG_ENTRY_ELF_SIZE 0x2000000

#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
#define EXT_MANIFEST_ELF_SIZE 0x2000000

#define SRAM_ALIAS_BASE 0x9E000000
#define SRAM_ALIAS_MASK 0xFF000000
Expand Down
14 changes: 14 additions & 0 deletions soc/xtensa/intel_adsp/cavs_v20/linker.ld
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Original file line number Diff line number Diff line change
Expand Up @@ -112,8 +112,15 @@ MEMORY
static_log_entries_seg (!ari) :
org = LOG_ENTRY_ELF_BASE,
len = LOG_ENTRY_ELF_SIZE
fw_metadata_seg (!ari) :
org = EXT_MANIFEST_ELF_BASE,
len = EXT_MANIFEST_ELF_SIZE
}

_EXT_MAN_ALIGN_ = 16;
EXTERN(ext_man_fw_ver)
EXTERN(ext_man_cavs_config)

PHDRS
{
vector_memory_lit_phdr PT_LOAD;
Expand Down Expand Up @@ -141,6 +148,7 @@ PHDRS

static_uuid_entries_phdr PT_NOTE;
static_log_entries_phdr PT_NOTE;
metadata_entries_phdr PT_NOTE;
}
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
Expand Down Expand Up @@ -532,4 +540,10 @@ SECTIONS
{
*(*.static_log*)
} > static_log_entries_seg :static_log_entries_phdr

.fw_metadata (COPY) : ALIGN(1024)
{
KEEP (*(.fw_metadata))
. = ALIGN(_EXT_MAN_ALIGN_);
} >fw_metadata_seg :metadata_entries_phdr
}
2 changes: 2 additions & 0 deletions soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
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Original file line number Diff line number Diff line change
Expand Up @@ -139,6 +139,8 @@
#define LOG_ENTRY_ELF_BASE 0x20000000
#define LOG_ENTRY_ELF_SIZE 0x2000000

#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
#define EXT_MANIFEST_ELF_SIZE 0x2000000

#define SRAM_ALIAS_BASE 0x9E000000
#define SRAM_ALIAS_MASK 0xFF000000
Expand Down
15 changes: 15 additions & 0 deletions soc/xtensa/intel_adsp/cavs_v25/linker.ld
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -112,6 +112,9 @@ MEMORY
static_log_entries_seg (!ari) :
org = LOG_ENTRY_ELF_BASE,
len = LOG_ENTRY_ELF_SIZE
fw_metadata_seg (!ari) :
org = EXT_MANIFEST_ELF_BASE,
len = EXT_MANIFEST_ELF_SIZE

lpsram_alt_reset_vec_seg :
org = LP_SRAM_ALT_RESET_VEC_BASE,
Expand Down Expand Up @@ -154,6 +157,7 @@ PHDRS

static_uuid_entries_phdr PT_NOTE;
static_log_entries_phdr PT_NOTE;
metadata_entries_phdr PT_NOTE;

lpsram_mem_phdr PT_LOAD;
sram_alt_fw_reset_vec_phdr PT_LOAD;
Expand Down Expand Up @@ -214,6 +218,11 @@ _memmap_cacheattr_intel_cavs25_adsp = 0xFF22FFF2;
#endif

PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs25_adsp);

_EXT_MAN_ALIGN_ = 16;
EXTERN(ext_man_fw_ver)
EXTERN(ext_man_cavs_config)

SECTIONS
{

Expand Down Expand Up @@ -600,4 +609,10 @@ SECTIONS
{
*(*.static_log*)
} > static_log_entries_seg :static_log_entries_phdr

.fw_metadata (COPY) : ALIGN(1024)
{
KEEP (*(.fw_metadata))
. = ALIGN(_EXT_MAN_ALIGN_);
} >fw_metadata_seg :metadata_entries_phdr
}