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Bluetooth: controller: nRF21540 FEM support for nRF52x and nRF53x Series #31336

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Merged
merged 6 commits into from
Apr 21, 2021
Merged

Bluetooth: controller: nRF21540 FEM support for nRF52x and nRF53x Series #31336

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a250f30
Bluetooth: controller: Adjust DPPI used for nRF53x
cvinayak Dec 3, 2020
0ab7313
Bluetooth: controller: GPIO PA/LNA support for nRF53x
cvinayak Dec 22, 2020
0f53b9c
Bluetooth: controller: Add PA/LNA pin range for nRF5340 SoC
bjornspock Jan 11, 2021
c28f326
Bluetooth: controller: Add Kconfig options for nRF21540 PDN and CSN pins
bjornspock Jan 11, 2021
1b0e05c
Bluetooth: controller: Add GPIO control for nRF21540 CSN and PDN lines
bjornspock Jan 13, 2021
440fc6f
Bluetooth: controller: nRF21540 FEM support for nRF52x Series
bjornspock Jan 14, 2021
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75 changes: 69 additions & 6 deletions subsys/bluetooth/controller/Kconfig.ll_sw_split
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Original file line number Diff line number Diff line change
Expand Up @@ -636,7 +636,7 @@ if BT_CTLR_GPIO_PA

config BT_CTLR_GPIO_PA_PIN
int "Power Amplifier GPIO pin number"
range 0 47 if SOC_NRF52840
range 0 47 if SOC_NRF52840 || SOC_NRF5340_CPUNET
range 0 31
help
GPIO Pin number connected to a Power Amplifier.
Expand All @@ -649,9 +649,9 @@ config BT_CTLR_GPIO_PA_POL_INV
config BT_CTLR_GPIO_PA_OFFSET
int "Time from PA ON to Tx ready"
default 5
range 0 10
range 0 15
help
Time before Tx ready to turn on PA.
Time before Tx ready to turn on PA in micro seconds.

endif # BT_CTLR_GPIO_PA

Expand All @@ -667,7 +667,7 @@ if BT_CTLR_GPIO_LNA

config BT_CTLR_GPIO_LNA_PIN
int "Low Noise Amplifier GPIO pin number"
range 0 47 if SOC_NRF52840
range 0 47 if SOC_NRF52840 || SOC_NRF5340_CPUNET
range 0 31
help
GPIO Pin number connected to a Low Noise Amplifier.
Expand All @@ -680,12 +680,57 @@ config BT_CTLR_GPIO_LNA_POL_INV
config BT_CTLR_GPIO_LNA_OFFSET
int "Time from LNA ON to Rx ready"
default 5
range 0 10
range 0 15
help
Time before Rx ready to turn on LNA.
Time before Rx ready to turn on LNA in micro seconds.

endif # BT_CTLR_GPIO_LNA

menuconfig BT_CTLR_FEM_NRF21540
bool "nRF21540 GPIO interface"
depends on !SOC_SERIES_NRF51X
select BT_CTLR_GPIO_PA
select BT_CTLR_GPIO_LNA
help
Enable PDN and CSN GPIO interface for the nRF21540. This allows
hardware designs using the nRF21540 to let the controller toggle
their state based on radio activity.

if BT_CTLR_FEM_NRF21540

config BT_CTLR_GPIO_PDN_PIN
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Forgive my ignorance, but are these Kconfig options being copy/pasted from somewhere else for a different SoC?

If not, they should definitely be in DT instead, along with the polarity (since we have the GPIO_ACTIVE_LOW flag in DTS), CSN pin, etc.

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I am not against use of DT, it is just that original controller contribution was before use of DT, and not all of controller has been ported to DT use.

they should definitely be in DT

Agree. As a subsequent PR, please do work on the port.

int "FEM PDN pin number"
range 0 47 if SOC_NRF52840 || SOC_NRF5340_CPUNET
range 0 31
help
GPIO Pin number connected to the PDN pin of the nRF21540 FEM.

config BT_CTLR_GPIO_PDN_POL_INV
bool "Inverted polarity for the PDN pin"
help
Enable inverted polarity (active low) for the PDN pin.

config BT_CTLR_GPIO_CSN_PIN
int "FEM CSN pin number"
range 0 47 if SOC_NRF52840 || SOC_NRF5340_CPUNET
range 0 31
help
GPIO Pin number connected to the CSN pin of the nRF21540 FEM.

config BT_CTLR_GPIO_CSN_POL_INV
bool "Inverted polarity for the CSN pin"
default y
help
Enable inverted polarity (active low) for the CSN pin.

config BT_CTLR_GPIO_PDN_CSN_OFFSET
int "Time from PDN and CSN toggle to PA/LNA pin toggle"
range 0 20
help
Time from PDN and CSN toggle to PA/LNA pin toggle in micro seconds.

endif # BT_CTLR_FEM_NRF21540

config BT_CTLR_PA_LNA_GPIOTE_CHAN
# Hidden "nRF5 GPIO PA/LNA GPIOTE Channel"
int
Expand All @@ -695,6 +740,24 @@ config BT_CTLR_PA_LNA_GPIOTE_CHAN
help
Select the nRF5 GPIOTE channel to use for PA/LNA GPIO feature.

config BT_CTLR_PDN_GPIOTE_CHAN
# Hidden "nRF5 GPIO FEM PDN GPIOTE Channel"
int
depends on SOC_FAMILY_NRF && BT_CTLR_FEM_NRF21540
default 4 if PWM_NRF5_SW
default 1
help
Select the nRF5 GPIOTE channel to use for FEM PDN GPIO pin toggle.

config BT_CTLR_CSN_GPIOTE_CHAN
# Hidden "nRF5 GPIO FEM CSN GPIOTE Channel"
int
depends on SOC_FAMILY_NRF && BT_CTLR_FEM_NRF21540
default 5 if PWM_NRF5_SW
default 2
help
Select the nRF5 GPIOTE channel to use for FEM CSN GPIO pin toggle.

comment "BLE Controller debug configuration"

config BT_CTLR_PROFILE_ISR
Expand Down
125 changes: 123 additions & 2 deletions subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.c
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Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,27 @@
#endif
#endif /* CONFIG_BT_CTLR_GPIO_LNA_PIN */

#if defined(CONFIG_BT_CTLR_GPIO_PDN_PIN)
#if ((CONFIG_BT_CTLR_GPIO_PDN_PIN) > 31)
#define NRF_GPIO_PDN NRF_P1
#define NRF_GPIO_PDN_PIN ((CONFIG_BT_CTLR_GPIO_PDN_PIN) - 32)
#else
#define NRF_GPIO_PDN NRF_P0
#define NRF_GPIO_PDN_PIN CONFIG_BT_CTLR_GPIO_PDN_PIN
#endif
#endif /* CONFIG_BT_CTLR_GPIO_PDN_PIN */

#if defined(CONFIG_BT_CTLR_GPIO_CSN_PIN)
#if ((CONFIG_BT_CTLR_GPIO_CSN_PIN) > 31)
#define NRF_GPIO_CSN NRF_P1
#define NRF_GPIO_CSN_PIN ((CONFIG_BT_CTLR_GPIO_CSN_PIN) - 32)
#else
#define NRF_GPIO_CSN NRF_P0
#define NRF_GPIO_CSN_PIN CONFIG_BT_CTLR_GPIO_CSN_PIN
#endif
#endif /* CONFIG_BT_CTLR_GPIO_CSN_PIN */


/* The following two constants are used in nrfx_glue.h for marking these PPI
* channels and groups as occupied and thus unavailable to other modules.
*/
Expand Down Expand Up @@ -97,6 +118,24 @@ void radio_setup(void)
radio_gpio_lna_off();
#endif /* CONFIG_BT_CTLR_GPIO_LNA_PIN */

#if defined(CONFIG_BT_CTLR_GPIO_PDN_PIN)
NRF_GPIO_PDN->DIRSET = BIT(NRF_GPIO_PDN_PIN);
#if defined(CONFIG_BT_CTLR_GPIO_PDN_POL_INV)
NRF_GPIO_PDN->OUTSET = BIT(NRF_GPIO_PDN_PIN);
#else
NRF_GPIO_PDN->OUTCLR = BIT(NRF_GPIO_PDN_PIN);
#endif
#endif /* CONFIG_BT_CTLR_GPIO_PDN_PIN */

#if defined(CONFIG_BT_CTLR_GPIO_CSN_PIN)
NRF_GPIO_CSN->DIRSET = BIT(NRF_GPIO_CSN_PIN);
#if defined(CONFIG_BT_CTLR_GPIO_CSN_POL_INV)
NRF_GPIO_CSN->OUTSET = BIT(NRF_GPIO_CSN_PIN);
#else
NRF_GPIO_CSN->OUTCLR = BIT(NRF_GPIO_CSN_PIN);
#endif
#endif /* CONFIG_BT_CTLR_GPIO_CSN_PIN */

hal_radio_ram_prio_setup();
}

Expand All @@ -122,6 +161,9 @@ void radio_reset(void)
#if defined(CONFIG_BT_CTLR_GPIO_PA_PIN) || defined(CONFIG_BT_CTLR_GPIO_LNA_PIN)
hal_palna_ppi_setup();
#endif
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
hal_fem_ppi_setup();
#endif
}

void radio_phy_set(uint8_t phy, uint8_t flags)
Expand Down Expand Up @@ -982,6 +1024,12 @@ void radio_gpio_pa_setup(void)
(GPIOTE_CONFIG_OUTINIT_Low <<
GPIOTE_CONFIG_OUTINIT_Pos);
#endif

#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
hal_pa_ppi_setup();
radio_gpio_pdn_setup();
radio_gpio_csn_setup();
#endif
}
#endif /* CONFIG_BT_CTLR_GPIO_PA_PIN */

Expand All @@ -1006,8 +1054,62 @@ void radio_gpio_lna_setup(void)
(GPIOTE_CONFIG_OUTINIT_Low <<
GPIOTE_CONFIG_OUTINIT_Pos);
#endif

#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
hal_lna_ppi_setup();
radio_gpio_pdn_setup();
radio_gpio_csn_setup();
#endif
}

#if defined(CONFIG_BT_CTLR_GPIO_PDN_PIN)
void radio_gpio_pdn_setup(void)
{
/* NOTE: With GPIO Pins above 31, left shift of
* CONFIG_BT_CTLR_GPIO_PA_PIN by GPIOTE_CONFIG_PSEL_Pos will
* set the NRF_GPIOTE->CONFIG[n].PORT to 1 (P1 port).
*/
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PDN_GPIOTE_CHAN] =
(GPIOTE_CONFIG_MODE_Task <<
GPIOTE_CONFIG_MODE_Pos) |
(CONFIG_BT_CTLR_GPIO_PDN_PIN <<
GPIOTE_CONFIG_PSEL_Pos) |
(GPIOTE_CONFIG_POLARITY_Toggle <<
GPIOTE_CONFIG_POLARITY_Pos) |
#if defined(CONFIG_BT_CTLR_GPIO_PDN_POL_INV)
(GPIOTE_CONFIG_OUTINIT_High <<
GPIOTE_CONFIG_OUTINIT_Pos);
#else
(GPIOTE_CONFIG_OUTINIT_Low <<
GPIOTE_CONFIG_OUTINIT_Pos);
#endif
}
#endif /* CONFIG_BT_CTLR_GPIO_PDN_PIN */

#if defined(CONFIG_BT_CTLR_GPIO_CSN_PIN)
void radio_gpio_csn_setup(void)
{
/* NOTE: With GPIO Pins above 31, left shift of
* CONFIG_BT_CTLR_GPIO_PA_PIN by GPIOTE_CONFIG_PSEL_Pos will
* set the NRF_GPIOTE->CONFIG[n].PORT to 1 (P1 port).
*/
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_CSN_GPIOTE_CHAN] =
(GPIOTE_CONFIG_MODE_Task <<
GPIOTE_CONFIG_MODE_Pos) |
(CONFIG_BT_CTLR_GPIO_CSN_PIN <<
GPIOTE_CONFIG_PSEL_Pos) |
(GPIOTE_CONFIG_POLARITY_Toggle <<
GPIOTE_CONFIG_POLARITY_Pos) |
#if defined(CONFIG_BT_CTLR_GPIO_CSN_POL_INV)
(GPIOTE_CONFIG_OUTINIT_High <<
GPIOTE_CONFIG_OUTINIT_Pos);
#else
(GPIOTE_CONFIG_OUTINIT_Low <<
GPIOTE_CONFIG_OUTINIT_Pos);
#endif
}
#endif /* CONFIG_BT_CTLR_GPIO_CSN_PIN */

void radio_gpio_lna_on(void)
{
#if defined(CONFIG_BT_CTLR_GPIO_LNA_POL_INV)
Expand All @@ -1030,15 +1132,34 @@ void radio_gpio_lna_off(void)
void radio_gpio_pa_lna_enable(uint32_t trx_us)
{
nrf_timer_cc_set(EVENT_TIMER, 2, trx_us);
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
nrf_timer_cc_set(EVENT_TIMER, 3, (trx_us -
CONFIG_BT_CTLR_GPIO_PDN_CSN_OFFSET));
hal_radio_nrf_ppi_channels_enable(BIT(HAL_ENABLE_PALNA_PPI) |
BIT(HAL_DISABLE_PALNA_PPI));
BIT(HAL_DISABLE_PALNA_PPI) |
BIT(HAL_ENABLE_FEM_PPI) |
BIT(HAL_DISABLE_FEM_PPI));
#else
hal_radio_nrf_ppi_channels_enable(BIT(HAL_ENABLE_PALNA_PPI) |
BIT(HAL_DISABLE_PALNA_PPI));
#endif
}

void radio_gpio_pa_lna_disable(void)
{
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
hal_radio_nrf_ppi_channels_disable(BIT(HAL_ENABLE_PALNA_PPI) |
BIT(HAL_DISABLE_PALNA_PPI));
BIT(HAL_DISABLE_PALNA_PPI) |
BIT(HAL_ENABLE_FEM_PPI) |
BIT(HAL_DISABLE_FEM_PPI));
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN] = 0;
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PDN_GPIOTE_CHAN] = 0;
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_CSN_GPIOTE_CHAN] = 0;
#else
hal_radio_nrf_ppi_channels_disable(BIT(HAL_ENABLE_PALNA_PPI) |
BIT(HAL_DISABLE_PALNA_PPI));
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN] = 0;
#endif
}
#endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */

Expand Down
2 changes: 2 additions & 0 deletions subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio.h
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Original file line number Diff line number Diff line change
Expand Up @@ -88,6 +88,8 @@ uint32_t radio_tmr_sample_get(void);

void radio_gpio_pa_setup(void);
void radio_gpio_lna_setup(void);
void radio_gpio_pdn_setup(void);
void radio_gpio_csn_setup(void);
void radio_gpio_lna_on(void);
void radio_gpio_lna_off(void);
void radio_gpio_pa_lna_enable(uint32_t trx_us);
Expand Down
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