soc: x86: add Lakemont SoC

arch/x86/Kconfig

@@ -48,6 +48,19 @@ config CPU_APOLLO_LAKE
 	help
 	  This option signifies the use of a CPU from the Apollo Lake family.
 
+config CPU_LAKEMONT
+	bool
+	select CPU_HAS_FPU
+	select ARCH_HAS_STACK_PROTECTION if X86_MMU
+	select ARCH_HAS_USERSPACE if X86_MMU
+	select X86_CPU_HAS_MMX
+	select X86_CPU_HAS_SSE
+	select X86_CPU_HAS_SSE2
+	select X86_CPU_HAS_SSE3
+	select X86_CPU_HAS_SSSE3
+	help
+	  This option signifies the use of a CPU from the Lakemont family.
+
 #
 # Configuration common to both IA32 and Intel64 sub-architectures.
 #
@@ -215,6 +228,7 @@ endchoice
 
 config ACPI
 	bool "ACPI (Advanced Configuration and Power Interface) support"
+	depends on X86_PC_COMPATIBLE
 	select ARCH_MAPS_ALL_RAM
 	help
 	  Allow retrieval of platform configuration at runtime.
@@ -230,8 +244,27 @@ config PCIE_MMIO_CFG
 config KERNEL_VM_SIZE
 	default 0xC0000000 if ACPI
 
+config X86_PC_COMPATIBLE
+	bool
+	default y
+	select ARCH_HAS_RESERVED_PAGE_FRAMES
+	help
+	  Hidden option to signal building for PC-compatible platforms
+	  with BIOS, ACPI, etc.
+
+config X86_MEMMAP
+	bool "Use memory map"
+	select ARCH_HAS_RESERVED_PAGE_FRAMES
+	help
+	  Enable the use of memory map to identify regions of memory.
+
+	  The memory map can be populated via Multiboot
+	  (CONFIG_MULTIBOOT=y and CONFIG_MULTIBOOT_MEMMAP=y) or
+	  can be manually defined via x86_memmap[].
+
 config X86_MEMMAP_ENTRIES
 	int "Number of memory map entries"
+	depends on X86_MEMMAP
 	range 1 256
 	default 1 if !MULTIBOOT_MEMMAP
 	default 64 if MULTIBOOT_MEMMAP
@@ -240,6 +273,7 @@ config X86_MEMMAP_ENTRIES
 
 config MULTIBOOT
 	bool "Generate multiboot header"
+	depends on X86_PC_COMPATIBLE
 	default y
 	help
 	  Embed a multiboot header in the output executable. This is used
@@ -260,6 +294,7 @@ config MULTIBOOT_INFO
 config MULTIBOOT_MEMMAP
 	bool "Use multiboot memory map if provided"
 	select MULTIBOOT_INFO
+	select X86_MEMMAP
 	help
 	  Use the multiboot memory map if the loader provides one.
 

arch/x86/core/CMakeLists.txt

@@ -9,11 +9,12 @@ if (CONFIG_COVERAGE)
 endif ()
 
 zephyr_library_sources(cpuhalt.c)
-zephyr_library_sources(memmap.c)
 zephyr_library_sources(prep_c.c)
 zephyr_library_sources(fatal.c)
 zephyr_library_sources(spec_ctrl.c)
 
+zephyr_library_sources_ifdef(CONFIG_X86_MEMMAP memmap.c)
+
 zephyr_library_sources_ifdef(CONFIG_PCIE pcie.c)
 zephyr_library_sources_ifdef(CONFIG_REBOOT_RST_CNT reboot_rst_cnt.c)
 zephyr_library_sources_ifdef(CONFIG_MULTIBOOT multiboot.c)

arch/x86/core/x86_mmu.c

@@ -1723,17 +1723,21 @@ static void mark_addr_page_reserved(uintptr_t addr, size_t len)
 	}
 }
 
-/* Selected on PC-like targets at the SOC level.
- *
- * Best is to do some E820 or similar enumeration to specifically identify
- * all page frames which are reserved by the hardware or firmware.
- *
- * For now, just reserve everything in the first megabyte of physical memory.
- */
 void arch_reserved_pages_update(void)
 {
+#ifdef CONFIG_X86_PC_COMPATIBLE
+	/*
+	 * Best is to do some E820 or similar enumeration to specifically
+	 * identify all page frames which are reserved by the hardware or
+	 * firmware. Or use x86_memmap[] with Multiboot if available.
+	 *
+	 * But still, reserve everything in the first megabyte of physical
+	 * memory on PC-compatible platforms.
+	 */
 	mark_addr_page_reserved(0, MB(1));
+#endif /* CONFIG_X86_PC_COMPATIBLE */
 
+#ifdef CONFIG_X86_MEMMAP
 	for (int i = 0; i < CONFIG_X86_MEMMAP_ENTRIES; i++) {
 		struct x86_memmap_entry *entry = &x86_memmap[i];
 
@@ -1755,6 +1759,7 @@ void arch_reserved_pages_update(void)
 
 		mark_addr_page_reserved(entry->base, entry->length);
 	}
+#endif /* CONFIG_X86_MEMMAP */
 }
 #endif /* CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES */
 

boards/x86/qemu_x86/Kconfig.board

@@ -13,3 +13,10 @@ config BOARD_QEMU_X86_64
 	select QEMU_TARGET
 	select X86_64
 	select HAS_COVERAGE_SUPPORT
+
+config BOARD_QEMU_X86_LAKEMONT
+	bool "QEMU x86 (Lakemont)"
+	depends on SOC_LAKEMONT
+	select QEMU_TARGET
+	select CPU_HAS_FPU
+	select HAS_COVERAGE_SUPPORT

boards/x86/qemu_x86/Kconfig.defconfig

@@ -35,3 +35,24 @@ config KERNEL_VM_SIZE
 	default 0x10000000 if ACPI
 
 endif # BOARD_QEMU_X86_64
+
+if BOARD_QEMU_X86_LAKEMONT
+
+config BUILD_OUTPUT_BIN
+	default n
+
+config BOARD
+	default "qemu_x86_lakemont"
+
+config KERNEL_VM_SIZE
+	default 0x400000
+
+config MULTIBOOT
+	# This is needed for QEMU to load the ELF image
+	default y
+
+config X86_PC_COMPATIBLE
+	# QEMU presents a PC-compatible machine
+	default y
+
+endif # BOARD_QEMU_X86_LAKEMONT

boards/x86/qemu_x86/board.cmake

@@ -26,9 +26,36 @@ else()
   math(EXPR QEMU_MEMORY_SIZE_MB "${CONFIG_SRAM_SIZE} / 1024")
 endif()
 
+set(QEMU_CPU_FLAGS "")
+if(CONFIG_X86_MMX)
+  string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "mmx")
+  string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "mmxext")
+endif()
+if(CONFIG_X86_SSE)
+  string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse")
+endif()
+if(CONFIG_X86_SSE2)
+  string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse2")
+endif()
+if(CONFIG_X86_SSE3)
+  string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "pni")
+endif()
+if(CONFIG_X86_SSSE3)
+  string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "ssse3")
+endif()
+if(CONFIG_X86_SSE41)
+  string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4.1")
+endif()
+if(CONFIG_X86_SSE42)
+  string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4.2")
+endif()
+if(CONFIG_X86_SSE4A)
+  string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4a")
+endif()
+
 set(QEMU_FLAGS_${ARCH}
   -m ${QEMU_MEMORY_SIZE_MB}
-  -cpu ${QEMU_CPU_TYPE_${ARCH}}
+  -cpu ${QEMU_CPU_TYPE_${ARCH}}${QEMU_CPU_FLAGS}
   -device isa-debug-exit,iobase=0xf4,iosize=0x04
   ${REBOOT_FLAG}
   -nographic

boards/x86/qemu_x86/qemu_x86_lakemont.dts

@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2021 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+
+#ifndef DT_DRAM_BASE
+#define DT_DRAM_BASE		0
+#endif
+#ifndef DT_DRAM_SIZE
+#define DT_DRAM_SIZE		DT_SIZE_K(4096)
+#endif
+
+#include <lakemont.dtsi>
+
+/ {
+	model = "QEMU X86 (Lakemont) emulator";
+	compatible = "qemu,x86_lakemont_emulator";
+
+	aliases {
+		uart-0 = &uart0;
+	};
+
+	chosen {
+		zephyr,sram = &dram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <DT_DRAM_BASE DT_DRAM_SIZE>;
+	};
+
+	soc {
+		uart0: uart@3f8 {
+			compatible = "ns16550";
+			reg = <0x000003f8 0x100>;
+			label = "UART_0";
+			clock-frequency = <1843200>;
+			interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+
+			status = "okay";
+		};
+
+		hpet: hpet@fed00000 {
+			label = "HPET";
+			compatible = "intel,hpet";
+			reg = <0xfed00000 0x400>;
+			interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
+			interrupt-parent = <&intc>;
+
+			status = "okay";
+		};
+	};
+};

boards/x86/qemu_x86/qemu_x86_lakemont.yaml

@@ -0,0 +1,13 @@
+identifier: qemu_x86_lakemont
+name: QEMU Emulation for X86 (Lakemont)
+type: qemu
+simulation: qemu
+arch: x86
+toolchain:
+  - zephyr
+  - xtools
+  - llvm
+testing:
+  default: true
+  only_tags:
+     - kernel

boards/x86/qemu_x86/qemu_x86_lakemont_defconfig

@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_LAKEMONT=y
+CONFIG_BOARD_QEMU_X86_LAKEMONT=y
+CONFIG_HPET_TIMER=y
+CONFIG_PIC_DISABLE=y
+CONFIG_LOAPIC=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
+CONFIG_TEST_RANDOM_GENERATOR=y
+CONFIG_X86_MMU=y
+CONFIG_DEBUG_INFO=y
+CONFIG_SCHED_SCALABLE=y
+CONFIG_WAITQ_SCALABLE=y
+CONFIG_X86_VERY_EARLY_CONSOLE=y
+CONFIG_QEMU_ICOUNT_SHIFT=5

dts/bindings/cpu/intel,lakemont.yml

@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Lakemont CPU
+
+compatible: "intel,lakemont"
+
+include: cpu.yaml

dts/x86/lakemont.dtsi

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2021 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/intel-ioapic.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,lakemont";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		reg = <0xfec00000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
+	/*
+	 * Platforms with Lakemont SoC can have different hardware
+	 * configurations. So RAM and peripherals need to be
+	 * defined in the board configuration's DTS.
+	 */
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+	};
+};

soc/x86/lakemont/CMakeLists.txt

@@ -0,0 +1,5 @@
+# Copyright (c) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_cc_option(-march=pentium)

soc/x86/lakemont/Kconfig.defconfig

@@ -0,0 +1,23 @@
+# Copyright (c) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_LAKEMONT
+
+config SOC
+	default "lakemont"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 32768
+
+# Can be enabled once UART is defined in board
+# configuration.
+config X86_VERY_EARLY_CONSOLE
+	default n
+
+# Target platforms are usually not PC-compatible
+# (e.g. without BIOS, ACPI, etc.).
+config X86_PC_COMPATIBLE
+	default n
+
+endif

soc/x86/lakemont/Kconfig.soc

@@ -0,0 +1,14 @@
+# Copyright (c) 2021 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_LAKEMONT
+	bool "Intel Lakemont SoC"
+	select X86
+	select CPU_LAKEMONT
+	select X86_MMU if FPU
+	select X86_SSE if FPU
+	select X86_SSE2 if FPU
+	select X86_SSE3 if FPU
+	select X86_SSSE3 if FPU
+	select ARCH_HAS_USERSPACE

soc/x86/lakemont/linker.ld

@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2011-2014, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/x86/memory.ld>
+#include <arch/x86/ia32/linker.ld>