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Merged
merged 4 commits into from
May 7, 2021
Merged

Add MIMXRT685 FlexSPI XIP support. #34502

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4ed468c
boards: arm: Enable FlexSPI driver on mimxrt685_evk.
saurabh-nxp Apr 22, 2021
999313e
drivers: flash: Enable FlexSPI XIP on mimxrt685_evk.
saurabh-nxp Apr 22, 2021
9ed5c43
drivers: memc: Update driver to support XIP on mimxrt685_evk.
saurabh-nxp Apr 30, 2021
02f245d
samples: fs: Enable littlefs sample for mimxrt685_evk.
saurabh-nxp May 5, 2021
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10 changes: 10 additions & 0 deletions boards/arm/mimxrt685_evk/Kconfig.defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,16 @@ config XTAL_SYS_CLK_HZ
config SYSOSC_SETTLING_US
default 260

config FLASH_MCUX_FLEXSPI_MX25UM51345G
default y if FLASH

config FLASH_MCUX_FLEXSPI_XIP
default y if FLASH

choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM
endchoice

if GPIO_MCUX_LPC

config GPIO_MCUX_LPC_PORT0
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24 changes: 24 additions & 0 deletions boards/arm/mimxrt685_evk/doc/index.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -71,6 +71,8 @@ features:
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | OctalSPI Flash |
+-----------+------------+-------------------------------------+
| USART | on-chip | serial port-polling |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
Expand Down Expand Up @@ -127,6 +129,28 @@ functionality of a pin.
+---------+-----------------+----------------------------+
| PIO0_9 | I2S | I2S DATAIN |
+---------+-----------------+----------------------------+
| PIO1_11 | FLEXSPI0B_DATA0 | OctalSPI Flash |
+---------+-----------------+----------------------------+
| PIO1_12 | FLEXSPI0B_DATA1 | OctalSPI Flash |
+---------+-----------------+----------------------------+
| PIO1_13 | FLEXSPI0B_DATA2 | OctalSPI Flash |
+---------+-----------------+----------------------------+
| PIO1_14 | FLEXSPI0B_DATA3 | OctalSPI Flash |
+---------+-----------------+----------------------------+
| PIO1_29 | FLEXSPI0B_SCLK | OctalSPI Flash |
+---------+-----------------+----------------------------+
| PIO2_12 | PIO2_12 | OctalSPI Flash |
+---------+-----------------+----------------------------+
| PIO2_17 | FLEXSPI0B_DATA4 | OctalSPI Flash |
+---------+-----------------+----------------------------+
| PIO2_18 | FLEXSPI0B_DATA5 | OctalSPI Flash |
+---------+-----------------+----------------------------+
| PIO2_19 | FLEXSPI0B_SS0_N | OctalSPI Flash |
+---------+-----------------+----------------------------+
| PIO2_22 | FLEXSPI0B_DATA6 | OctalSPI Flash |
+---------+-----------------+----------------------------+
| PIO2_23 | FLEXSPI0B_DATA7 | OctalSPI Flash |
+---------+-----------------+----------------------------+

System Clock
============
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24 changes: 24 additions & 0 deletions boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts
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Expand Up @@ -170,6 +170,30 @@ i2s1: &flexcomm3 {
dma-names = "tx";
};

&flexspi {
reg = <0x50134000 0x4000>, <0x18000000 DT_SIZE_M(64)>;
mx25um51345g: mx25um51345g@2 {
compatible = "nxp,imx-flexspi-mx25um51345g";
size = <536870912>;
label = "MX25UM51345G";
reg = <2>;
spi-max-frequency = <200000000>;
status = "okay";
jedec-id = [c2 81 3a];

partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

storage_partition: partition@3f00000 {
label = "storage";
reg = <0x03f00000 DT_SIZE_M(1)>;
};
};
};
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@mmahadevan108 mmahadevan108 May 5, 2021

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This commit can be squashed with the earlier one that changes board dts file

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@saurabh-nxp saurabh-nxp May 6, 2021

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After adding storage_partition to dts still facing an issue to get littlefs running. If able to get it to work will squash commits.

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@MaureenHelm MaureenHelm May 6, 2021

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The sample is failing because flash_area is trying to use the flexspi device with the flash API, when it should use the mx25um51345g device instead. You can fix this by moving the partitions section inside the mx25um51345g node.

Area 0 at 0x3f00000 on MX25UM51345G for 1048576 bytes
/lfs mount: 0
/lfs: bsize = 16 ; frsize = 4096 ; blocks = 256 ; bfree = 254
/lfs/boot_count stat: 0
        fn 'boot_count' siz 4
/lfs/boot_count read count 1: 4
/lfs/boot_count seek start: 0
/lfs/boot_count write new boot count 2: 4
/lfs/boot_count close: 0
/lfs opendir: 0
  F 4 boot_count
End of files
/lfs unmount: 0
[00:16:13.131,023] <inf> littlefs: LittleFS version 2.2, disk version 2.0
[00:16:13.133,602] <inf> littlefs: FS at MX25UM51345G:0x3f00000 is 256 0x1000-byte blocks with 512 e
[00:16:13.133,605] <inf> littlefs: sizes: rd 16 ; pr 16 ; ca 64 ; la 32
[00:16:13.133,876] <inf> littlefs: /lfs mounted
[00:16:13.161,600] <inf> littlefs: /lfs unmounted

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@saurabh-nxp saurabh-nxp May 6, 2021

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Thank you! Done.

};

&gpio0 {
status = "okay";
};
Expand Down
233 changes: 233 additions & 0 deletions boards/arm/mimxrt685_evk/pinmux.c
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Expand Up @@ -396,6 +396,239 @@ static int mimxrt685_evk_pinmux_init(const struct device *dev)
/* PORT0 PIN9 (coords: L3) is configured as FC1_RXD_SDA_MOSI_DATA */
IOPCTL_PinMuxSet(IOPCTL, 0U, 9U, port0_pin9_config);

#endif

#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay) && CONFIG_FLASH
const uint32_t port1_pin11_config = (/* Pin is configured as FLEXSPI0B_DATA0 */
IOPCTL_PIO_FUNC6 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Full drive enable */
IOPCTL_PIO_FULLDRIVE_EN |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT1 PIN11 (coords: L2) is configured as FLEXSPI0B_DATA0 */
IOPCTL_PinMuxSet(IOPCTL, 1U, 11U, port1_pin11_config);

const uint32_t port1_pin12_config = (/* Pin is configured as FLEXSPI0B_DATA1 */
IOPCTL_PIO_FUNC6 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Full drive enable */
IOPCTL_PIO_FULLDRIVE_EN |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT1 PIN12 (coords: M2) is configured as FLEXSPI0B_DATA1 */
IOPCTL_PinMuxSet(IOPCTL, 1U, 12U, port1_pin12_config);

const uint32_t port1_pin13_config = (/* Pin is configured as FLEXSPI0B_DATA2 */
IOPCTL_PIO_FUNC6 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Full drive enable */
IOPCTL_PIO_FULLDRIVE_EN |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT1 PIN13 (coords: N1) is configured as FLEXSPI0B_DATA2 */
IOPCTL_PinMuxSet(IOPCTL, 1U, 13U, port1_pin13_config);

const uint32_t port1_pin14_config = (/* Pin is configured as FLEXSPI0B_DATA3 */
IOPCTL_PIO_FUNC6 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Full drive enable */
IOPCTL_PIO_FULLDRIVE_EN |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT1 PIN14 (coords: N2) is configured as FLEXSPI0B_DATA3 */
IOPCTL_PinMuxSet(IOPCTL, 1U, 14U, port1_pin14_config);

const uint32_t port1_pin29_config = (/* Pin is configured as FLEXSPI0B_SCLK */
IOPCTL_PIO_FUNC5 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Full drive enable */
IOPCTL_PIO_FULLDRIVE_EN |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT1 PIN29 (coords: U3) is configured as FLEXSPI0B_SCLK */
IOPCTL_PinMuxSet(IOPCTL, 1U, 29U, port1_pin29_config);

const uint32_t port2_pin12_config = (/* Pin is configured as PIO2_12 */
IOPCTL_PIO_FUNC0 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Disable input buffer function */
IOPCTL_PIO_INBUF_DI |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT2 PIN12 (coords: T3) is configured as PIO2_12 */
IOPCTL_PinMuxSet(IOPCTL, 2U, 12U, port2_pin12_config);

const uint32_t port2_pin17_config = (/* Pin is configured as FLEXSPI0B_DATA4 */
IOPCTL_PIO_FUNC6 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Full drive enable */
IOPCTL_PIO_FULLDRIVE_EN |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT2 PIN17 (coords: U1) is configured as FLEXSPI0B_DATA4 */
IOPCTL_PinMuxSet(IOPCTL, 2U, 17U, port2_pin17_config);

const uint32_t port2_pin18_config = (/* Pin is configured as FLEXSPI0B_DATA5 */
IOPCTL_PIO_FUNC6 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Full drive enable */
IOPCTL_PIO_FULLDRIVE_EN |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT2 PIN18 (coords: R2) is configured as FLEXSPI0B_DATA5 */
IOPCTL_PinMuxSet(IOPCTL, 2U, 18U, port2_pin18_config);

const uint32_t port2_pin19_config = (/* Pin is configured as FLEXSPI0B_SS0_N */
IOPCTL_PIO_FUNC6 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Full drive enable */
IOPCTL_PIO_FULLDRIVE_EN |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT2 PIN19 (coords: T2) is configured as FLEXSPI0B_SS0_N */
IOPCTL_PinMuxSet(IOPCTL, 2U, 19U, port2_pin19_config);

const uint32_t port2_pin22_config = (/* Pin is configured as FLEXSPI0B_DATA6 */
IOPCTL_PIO_FUNC6 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Full drive enable */
IOPCTL_PIO_FULLDRIVE_EN |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT2 PIN22 (coords: P3) is configured as FLEXSPI0B_DATA6 */
IOPCTL_PinMuxSet(IOPCTL, 2U, 22U, port2_pin22_config);

const uint32_t port2_pin23_config = (/* Pin is configured as FLEXSPI0B_DATA7 */
IOPCTL_PIO_FUNC6 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Full drive enable */
IOPCTL_PIO_FULLDRIVE_EN |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT2 PIN23 (coords: P5) is configured as FLEXSPI0B_DATA7 */
IOPCTL_PinMuxSet(IOPCTL, 2U, 23U, port2_pin23_config);
#endif

return 0;
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12 changes: 11 additions & 1 deletion drivers/flash/CMakeLists.txt
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Expand Up @@ -18,11 +18,16 @@ zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NIOS2_QSPI soc_flash_nios2_qspi.c)
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_GECKO flash_gecko.c)
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_RV32M1 soc_flash_rv32m1.c)
zephyr_library_sources_ifdef(CONFIG_FLASH_STM32_QSPI flash_stm32_qspi.c)
zephyr_library_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_MX25UM51345G flash_mcux_flexspi_mx25um51345g.c)
zephyr_library_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_NOR flash_mcux_flexspi_nor.c)
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_ESP32 flash_esp32.c)

if(CONFIG_FLASH_MCUX_FLEXSPI_XIP)
zephyr_code_relocate(flash_mcux_flexspi_nor.c ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT)
if(CONFIG_FLASH_MCUX_FLEXSPI_MX25UM51345G)
zephyr_code_relocate(flash_mcux_flexspi_mx25um51345g.c ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT)
else()
zephyr_code_relocate(flash_mcux_flexspi_nor.c ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT)
endif()
endif()

if(CONFIG_SOC_FLASH_STM32)
Expand All @@ -46,6 +51,11 @@ zephyr_include_directories_ifdef(
${ZEPHYR_BASE}/drivers/memc
)

zephyr_include_directories_ifdef(
CONFIG_FLASH_MCUX_FLEXSPI_MX25UM51345G
${ZEPHYR_BASE}/drivers/memc
)

zephyr_include_directories_ifdef(
CONFIG_SOC_FLASH_NRF_RADIO_SYNC_TICKER
${ZEPHYR_BASE}/subsys/bluetooth
Expand Down
11 changes: 9 additions & 2 deletions drivers/flash/Kconfig.mcux
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Expand Up @@ -34,10 +34,17 @@ config FLASH_MCUX_FLEXSPI_NOR
select MEMC
select MEMC_MCUX_FLEXSPI

config FLASH_MCUX_FLEXSPI_MX25UM51345G
bool "MCUX FlexSPI MX25UM51345G driver"
select FLASH_HAS_PAGE_LAYOUT
select FLASH_HAS_DRIVER_ENABLED
select MEMC
select MEMC_MCUX_FLEXSPI

config FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
bool "MCUX FlexSPI NOR write RAM buffer"
default y
depends on FLASH_MCUX_FLEXSPI_NOR
depends on (FLASH_MCUX_FLEXSPI_NOR || FLASH_MCUX_FLEXSPI_MX25UM51345G)
help
Copy the data to a RAM buffer before writing it to the flash.
This prevents faults when the data to write would be located on the
Expand All @@ -46,7 +53,7 @@ config FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
config FLASH_MCUX_FLEXSPI_XIP
bool "MCUX FlexSPI flash access with xip"
depends on MEMC_MCUX_FLEXSPI
depends on (CODE_FLEXSPI || CODE_FLEXSPI2)
depends on (CODE_FLEXSPI || CODE_FLEXSPI2 || SOC_SERIES_IMX_RT6XX)
select XIP
help
Allows using the flash API while running in XIP.
Expand Down
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