Enable CAN peripheral on STM32G0

boards/arm/nucleo_g0b1re/doc/index.rst

@@ -96,6 +96,8 @@ The Zephyr nucleo_g0b1re board configuration supports the following hardware fea
 +-----------+------------+-------------------------------------+
 | SPI       | on-chip    | spi                                 |
 +-----------+------------+-------------------------------------+
+| CAN       | on-chip    | CAN 2.0 and CAN FD compliant        |
++-----------+------------+-------------------------------------+
 | CLOCK     | on-chip    | reset and clock control             |
 +-----------+------------+-------------------------------------+
 | COUNTER   | on-chip    | rtc                                 |
@@ -131,6 +133,7 @@ Default Zephyr Peripheral Mapping:
 - I2C2 SCL/SDA : PA11/PA12
 - SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI)
 - SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15
+- CAN1 TX/RX : PA11/PA12
 - USER_PB   : PC13
 - LD4       : PA5
 - PWM       : PA6

boards/arm/nucleo_g0b1re/nucleo_g0b1re.dts

@@ -20,6 +20,7 @@
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 		zephyr,code-partition = &slot0_partition;
+		zephyr,can-primary = &can1;
 	};
 
 	leds {
@@ -128,6 +129,36 @@
 	pinctrl-0 = <&dac1_out1_pa4>;
 };
 
+&shared_irq21 {
+	status = "okay";
+};
+
+&shared_irq22 {
+	status = "okay";
+};
+
+&can1 {
+	pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
+	bus-speed = <125000>;
+	sjw = <1>;
+	sample-point = <875>;
+	bus-speed-data = <1000000>;
+	sjw-data = <1>;
+	sample-point-data = <875>;
+	status = "okay";
+};
+
+&can2 {
+	pinctrl-0 = <&fdcan2_rx_pb5 &fdcan2_tx_pb6>;
+	bus-speed = <125000>;
+	sjw = <1>;
+	sample-point = <875>;
+	bus-speed-data = <1000000>;
+	sjw-data = <1>;
+	sample-point-data = <875>;
+	status = "okay";
+};
+
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";

boards/arm/nucleo_g0b1re/nucleo_g0b1re.yaml

@@ -18,3 +18,5 @@ supported:
   - spi
   - nvs
   - dma
+  - can
+  - canfd

drivers/can/can_stm32fd.c

@@ -10,6 +10,7 @@
 #include <stm32_ll_rcc.h>
 #include "can_stm32fd.h"
 #include <pinmux/pinmux_stm32.h>
+#include <shared_irq.h>
 
 #include <logging/log.h>
 LOG_MODULE_DECLARE(can_driver, CONFIG_CAN_LOG_LEVEL);
@@ -208,18 +209,22 @@ static const struct can_driver_api can_api_funcs = {
 #endif
 };
 
+/*
+ * If a shared-irq with matching name exists and has status okay use the
+ * shared-irq driver, otherwise, connect to normal IRQ.
+ */
 #define CAN_STM32FD_IRQ_CFG_FUNCTION(inst)                                     \
 static void config_can_##inst##_irq(void)                                      \
 {                                                                              \
 	LOG_DBG("Enable CAN" #inst " IRQ");                                    \
-	IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_0, irq),                    \
-		    DT_INST_IRQ_BY_NAME(inst, line_0, priority),               \
-		    can_stm32fd_line_0_isr, DEVICE_DT_INST_GET(inst), 0);      \
-	irq_enable(DT_INST_IRQ_BY_NAME(inst, line_0, irq));                    \
-	IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, line_1, irq),                    \
-		    DT_INST_IRQ_BY_NAME(inst, line_1, priority),               \
-		    can_stm32fd_line_1_isr, DEVICE_DT_INST_GET(inst), 0);      \
-	irq_enable(DT_INST_IRQ_BY_NAME(inst, line_1, irq));                    \
+	SHARED_IRQ_CONNECT_IRQ_BY_NAME_COND(DT_DRV_INST(inst), line_0,         \
+						 can_stm32fd_line_0_isr,       \
+						 DEVICE_DT_INST_GET(inst), 0); \
+	SHARED_IRQ_CONNECT_IRQ_BY_NAME_COND(DT_DRV_INST(inst), line_1,         \
+						 can_stm32fd_line_1_isr,       \
+						 DEVICE_DT_INST_GET(inst), 0); \
+	SHARED_IRQ_ENABLE_BY_NAME_COND(DT_DRV_INST(inst), line_0);             \
+	SHARED_IRQ_ENABLE_BY_NAME_COND(DT_DRV_INST(inst), line_1);             \
 }
 
 #ifdef CONFIG_CAN_FD_MODE

drivers/interrupt_controller/Kconfig.shared_irq

@@ -5,6 +5,7 @@
 
 menuconfig SHARED_IRQ
 	bool "Shared interrupt driver"
+	default $(dt_compat_enabled,shared-irq)
 	help
 	  Include shared interrupt support in system. Shared interrupt
 	  support is NOT required in most systems. If in doubt answer no.

dts/arm/st/g0/stm32g0b1.dtsi

@@ -104,5 +104,69 @@
 			dma-channels = <12>;
 			dma-requests = <73>;
 		};
+
+		can {
+			compatible = "bosch,m-can-base";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			std-filter-elements = <28>;
+			ext-filter-elements = <8>;
+			rx-fifo0-elements = <3>;
+			rx-fifo1-elements = <3>;
+			rx-buffer-elements = <0>;
+			tx-buffer-elements = <3>;
+
+			can1: can@40006400 {
+				compatible = "st,stm32-fdcan";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x40006400 0x400>, <0x4000B400 0x350>;
+				reg-names = "m_can", "message_ram";
+				interrupts = <21 0>, <22 0>;
+				interrupt-names = "LINE_0", "LINE_1";
+				shared-irqs = <&shared_irq21 &shared_irq22>;
+				shared-irq-names = "LINE_0", "LINE_1";
+				status = "disabled";
+				label = "CAN_1";
+			};
+
+			can2: can@40006800 {
+				compatible = "st,stm32-fdcan";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x40006800 0x400>, <0x4000B750 0x350>;
+				reg-names = "m_can", "message_ram";
+				interrupts = <21 0>, <22 0>;
+				interrupt-names = "LINE_0", "LINE_1";
+				shared-irqs = <&shared_irq21 &shared_irq22>;
+				shared-irq-names = "LINE_0", "LINE_1";
+				status = "disabled";
+				label = "CAN_2";
+			};
+		};
+	};
+
+	shared_irq21: shared_irq21 {
+		compatible = "shared-irq";
+		interrupt-parent = <&nvic>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupts = <21 0>;
+		interrupt-names = "tim16_fdcan_it0";
+		#shared-irq-cells = <0>;
+		status = "disabled";
+		label = "SHARED_IRQ_21";
+	};
+
+	shared_irq22: shared_irq22 {
+		compatible = "shared-irq";
+		interrupt-parent = <&nvic>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupts = <22 0>;
+		interrupt-names = "tim17_fdcan_it1";
+		#shared-irq-cells = <0>;
+		status = "disabled";
+		label = "SHARED_IRQ_22";
 	};
 };

dts/bindings/can/st,stm32-fdcan.yaml

@@ -14,3 +14,22 @@ properties:
 
         For example the can1 would be
            pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
+
+    shared-irq-names:
+      type: string-array
+      required: false
+      description: |
+        Name of each shared-irq in shared-irqs.
+        Required if shared-irqs are used and interrupts are chosen by name.
+
+    shared-irqs:
+      type: phandle-array
+      required: false
+      description: |
+        To avoid interrupt conflicts shared-irq nodes can be referenced.
+        In case the referenced shared_irq phandles have status okay the driver
+        registers the isr with the shared_irq instance instead of connecting to
+        the irq.
+
+        Example for stm32g0 would be
+              shared-irqs = <&shared_irq21 &shared_irq22>;