boards: Add support GigaDevice GD32V SoC

CODEOWNERS

@@ -74,6 +74,7 @@
 /soc/riscv/openisa*/                      @dleach02
 /soc/riscv/riscv-privilege/andes_v5/      @cwshu @kevinwang821020 @jimmyzhe
 /soc/riscv/riscv-privilege/neorv32/       @henrikbrixandersen
+/soc/riscv/riscv-privilege/gd32vf103/     @soburi
 /soc/x86/                                 @dcpleung @nashif @jenmwms @aasthagr
 /arch/xtensa/                             @dcpleung @andyross @nashif
 /soc/xtensa/                              @dcpleung @andyross @nashif
@@ -152,6 +153,7 @@
 /boards/riscv/rv32m1_vega/                @dleach02
 /boards/riscv/beaglev_starlight_jh7100/   @rajnesh-kanwal
 /boards/riscv/adp_xc7k_ae350/             @cwshu @kevinwang821020 @jimmyzhe
+/boards/riscv/longan_nano/                @soburi
 /boards/riscv/neorv32/                    @henrikbrixandersen
 /boards/shields/                          @erwango
 /boards/shields/atmel_rf2xx/              @nandojve
@@ -274,6 +276,7 @@
 /drivers/interrupt_controller/            @dcpleung @nashif
 /drivers/interrupt_controller/intc_gic.c  @stephanosio
 /drivers/interrupt_controller/*esp32*     @glaubermaroto
+/drivers/interrupt_controller/intc_nuclei_eclic.c  @soburi
 /drivers/ipm/ipm_mhu*                     @karl-zh
 /drivers/ipm/Kconfig.nrfx                 @masz-nordic
 /drivers/ipm/Kconfig.nrfx_ipc_channel     @masz-nordic

MAINTAINERS.yml

@@ -1380,14 +1380,18 @@ GD32 Platforms:
     maintainers:
         - nandojve
         - gmarull
+    collaborators:
+        - soburi
     files:
         - boards/arm/gd32*/
+        - boards/riscv/longan_nano/
         - drivers/*/*gd32*/
         - drivers/*/*gd32*
-        - dts/arm/gigadevice/
+        - dts/*/gigadevice/
         - dts/bindings/*/*gd32*
         - modules/hal_gigadevice/
         - soc/arm/gigadevice/
+        - soc/riscv/riscv-privilege/gd32vf103/
         - scripts/west_commands/*/*gd32*
     labels:
         - "platform: GD32"

arch/riscv/Kconfig

@@ -102,6 +102,13 @@ config RISCV_SOC_INTERRUPT_INIT
 	  Enable SOC-based interrupt initialization
 	  (call soc_interrupt_init, within _IntLibInit when enabled)
 
+config RISCV_SOC_MCAUSE_EXCEPTION_MASK
+	hex
+	default 0x7FFFFFFFFFFFFFFF if 64BIT
+	default 0x7FFFFFFF
+	help
+	  Specify the bits to use for exception code in mcause register.
+
 config RISCV_GENERIC_TOOLCHAIN
 	bool "Compile using generic riscv32 toolchain"
 	default y

boards/riscv/longan_nano/Kconfig.board

@@ -0,0 +1,10 @@
+# Copyright (c) 2021 Tokita, Hiroshi <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_LONGAN_NANO
+	bool "Sipeed Longan Nano target"
+	depends on SOC_GD32VF103
+
+config BOARD_LONGAN_NANO_LITE
+	bool "Sipeed Longan Nano Lite target"
+	depends on SOC_GD32VF103

boards/riscv/longan_nano/Kconfig.defconfig

@@ -0,0 +1,11 @@
+# Sipeed longan nano Development Board Configuration
+
+# Copyright (c) 2021 Tokita, Hiroshi <[email protected]>
+
+if BOARD_LONGAN_NANO || BOARD_LONGAN_NANO_LITE
+
+config BOARD
+	default "longan_nano" if BOARD_LONGAN_NANO
+	default "longan_nano_lite" if BOARD_LONGAN_NANO_LITE
+
+endif # BOARD_LONGAN_NANO || BOARD_LONGAN_NANO_LITE

boards/riscv/longan_nano/board.cmake

@@ -0,0 +1,10 @@
+# Copyright (c) 2021 Tokita, Hiroshi <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(openocd --cmd-pre-init "source [find target/gd32vf103.cfg]")
+
+board_runner_args(openocd "--cmd-pre-load=gd32vf103-pre-load")
+board_runner_args(openocd "--cmd-load=gd32vf103-load")
+board_runner_args(openocd "--cmd-post-verify=gd32vf103-post-verify")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/riscv/longan_nano/doc/index.rst

@@ -0,0 +1,64 @@
+.. _longan_nano:
+
+Sipeed Longan Nano
+##################
+
+Overview
+********
+
+The Sipeed Longan Nano and Longan Nano Lite is an simple and tiny development board with
+an GigaDevice GD32VF103 SoC that based on N200 RISC-V IP core by Nuclei system technology.
+More information can be found on:
+
+- `Sipeed Longan website <https://longan.sipeed.com/en/>`_
+- `GD32VF103 datasheet <https://www.gigadevice.com/datasheet/gd32vf103xxxx-datasheet/>`_
+- `GD32VF103 user manual <http://www.gd32mcu.com/data/documents/shujushouce/GD32VF103_User_Manual_EN_V1.2.pdf>`_
+- `Nuclei website <https://www.nucleisys.com/download.php>`_
+- `Nuclei Bumblebee core documents <https://github.com/nucleisys/Bumblebee_Core_Doc>`_
+- `Nuclei ISA Spec <https://doc.nucleisys.com/nuclei_spec/>`_
+
+Programming and debugging
+*************************
+
+Building
+========
+
+Applications for the ``logan_nano`` board configuration can be built as usual
+(see :ref:`build_an_application`) using the corresponding board name:
+
+.. zephyr-app-commands::
+   :board: logan_nano
+   :goals: build
+
+Flashing
+========
+
+In order to upload the application to the device, you'll need OpenOCD with
+GD32V support. Download the tarball for your OS from the
+`SiPEED longan nano download site
+<http://dl.sipeed.com/LONGAN/platformio/dl-packages/>`_ and extract it.
+
+The Zephyr SDK uses a bundled version of OpenOCD by default. You can
+overwrite that behavior by adding the
+``-DOPENOCD=<path/to/riscv-openocd/bin/openocd>``
+parameter when building:
+
+.. zephyr-app-commands::
+   :board: longan_nano
+   :goals: build
+   :gen-args: -DOPENOCD=<path/to/riscv-openocd/bin/openocd>
+
+When using a custom toolchain it should be enough to have the downloaded
+version of the binary in your ``PATH``.
+
+Now you can flash the application as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details):
+
+.. code-block:: console
+
+   west flash
+
+Debugging
+=========
+
+Refer to the detailed overview about :ref:`application_debugging`.

boards/riscv/longan_nano/longan_nano-pinctrl.dtsi

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021, TOKITA Hiroshi
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/gd32vf103c(b-8)xx-pinctrl.h>
+
+&pinctrl {
+	usart0_default: usart0_default {
+		group1 {
+			pinmux = <USART0_TX_PA9_NORMP>, <USART0_RX_PA10_NORMP>;
+		};
+	};
+};

boards/riscv/longan_nano/longan_nano.dts

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021 Tokita, Hiroshi <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <gigadevice/gd32vf103Xb.dtsi>
+#include "longan_nano-pinctrl.dtsi"
+
+/ {
+	model = "Sipeed Longan Nano";
+	compatible = "sipeed,longan_nano";
+
+	chosen {
+		zephyr,console = &usart0;
+		zephyr,shell-uart = &usart0;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+};
+
+&usart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&usart0_default>;
+	pinctrl-names = "default";
+};

boards/riscv/longan_nano/longan_nano.yaml

@@ -0,0 +1,9 @@
+identifier: longan_nano
+name: Sipeed Longan Nano
+type: mcu
+arch: riscv32
+toolchain:
+  - zephyr
+  - xtools
+flash: 128
+ram: 32

boards/riscv/longan_nano/longan_nano_defconfig

@@ -0,0 +1,21 @@
+# Sipeed longan nano Development Board Configuration
+#
+# Copyright (c) 2021 Tokita, Hiroshi <[email protected]>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SOC_SERIES_GD32VF103=y
+CONFIG_SOC_GD32VF103=y
+CONFIG_GD32_HXTAL_8MHZ=y
+
+# enable machine timer
+CONFIG_RISCV_MACHINE_TIMER=y
+
+# enable uart driver
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

boards/riscv/longan_nano/longan_nano_lite.dts

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021 Tokita, Hiroshi <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <gigadevice/gd32vf103X8.dtsi>
+#include "longan_nano-pinctrl.dtsi"
+
+/ {
+	model = "Sipeed Longan Nano Lite";
+	compatible = "sipeed,longan_nano_lite";
+
+	chosen {
+		zephyr,console = &usart0;
+		zephyr,shell-uart = &usart0;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+};
+
+&usart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&usart0_default>;
+	pinctrl-names = "default";
+};

boards/riscv/longan_nano/longan_nano_lite.yaml

@@ -0,0 +1,9 @@
+identifier: longan_nano_lite
+name: Sipeed Longan Nano Lite
+type: mcu
+arch: riscv32
+toolchain:
+  - zephyr
+  - xtools
+flash: 64
+ram: 20

boards/riscv/longan_nano/longan_nano_lite_defconfig

@@ -0,0 +1,21 @@
+# Sipeed Longan Nano Lite board Configuration
+#
+# Copyright (c) 2021 Tokita, Hiroshi <[email protected]>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SOC_SERIES_GD32VF103=y
+CONFIG_SOC_GD32VF103=y
+CONFIG_GD32_HXTAL_8MHZ=y
+
+# enable machine timer
+CONFIG_RISCV_MACHINE_TIMER=y
+
+# enable uart driver
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

boards/riscv/longan_nano/support/openocd.cfg

@@ -0,0 +1,33 @@
+# Copyright (c) 2021 Tokita, Hiroshi <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+interface ftdi
+
+ftdi_device_desc "Dual RS232"
+#ftdi_device_desc "Sipeed-Debug"
+#ftdi_device_desc "JTAG Debugger"
+
+ftdi_vid_pid 0x0403 0x6010
+#ftdi_channel 0
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
+
+adapter_khz 2000
+transport select jtag
+
+proc gd32vf103-pre-load {} {
+	halt
+}
+
+proc gd32vf103-load {file} {
+	flash protect 0 0 last off
+	flash write_image erase $file
+}
+
+
+proc gd32vf103-post-verify {} {
+	mww 0xe004200c 0x4b5a6978
+	mww 0xe0042008 0x01
+	resume
+}

drivers/interrupt_controller/CMakeLists.txt

@@ -26,3 +26,4 @@ zephyr_library_sources_ifdef(CONFIG_INTC_ESP32              intc_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_INTC_ESP32C3            intc_esp32c3.c)
 zephyr_library_sources_ifdef(CONFIG_SWERV_PIC               intc_swerv_pic.c)
 zephyr_library_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ      intc_vexriscv_litex.c)
+zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC            intc_nuclei_eclic.c)

drivers/interrupt_controller/Kconfig

@@ -73,4 +73,6 @@ source "drivers/interrupt_controller/Kconfig.esp32c3"
 
 source "drivers/interrupt_controller/Kconfig.xec"
 
+source "drivers/interrupt_controller/Kconfig.eclic"
+
 endmenu

drivers/interrupt_controller/Kconfig.eclic

@@ -0,0 +1,18 @@
+# Nuclei ECLIC interrupt-controller configuration
+
+# Copyright (c) 2021 Tokita, Hiroshi <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+DT_COMPAT_NUCLEI_ECLIC = nuclei,eclic
+
+config HAS_NUCLEI_ECLIC
+	bool
+	help
+	  Indicate that the platform has ECLIC.
+
+config NUCLEI_ECLIC
+	bool "Enhanced Core Local Interrupt Controller (ECLIC)"
+	default $(dt_compat_enabled,$(DT_COMPAT_NUCLEI_ECLIC))
+	depends on HAS_NUCLEI_ECLIC
+	help
+	  Interrupt controller for Nuclei SoC core.