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linker: aarch32: automatic derivation of region names from devicetree nodes #36196

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linker: aarch32: automatic derivation of region names from devicetree nodes #36196

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36fb50d
devicetree: add label to `sramN` nodes
Jun 12, 2021
4a05b9f
devicetree: add label to `dtcm` nodes
Jun 12, 2021
a108f98
devicetree: add label to `itcm` nodes
Jun 12, 2021
ef0f74f
devicetree: arm: ti: rename `ti_ccfg` partition
Jun 12, 2021
a6e956f
linker: aarch32: derive region names from DT nodes
Jun 12, 2021
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2 changes: 2 additions & 0 deletions boards/arm/arty/arty_a7_arm_designstart_m1.dts
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Expand Up @@ -28,11 +28,13 @@
itcm: memory@0 {
compatible = "arm,itcm";
reg = <0x00000000 DT_SIZE_K(64)>;
label = "ITCM";
};

dtcm: memory@20000000 {
compatible = "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(32)>;
label = "DTCM";
};

bram0: memory@60000000 {
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2 changes: 2 additions & 0 deletions boards/arm/arty/arty_a7_arm_designstart_m3.dts
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itcm: memory@0 {
compatible = "arm,itcm";
reg = <0x00000000 DT_SIZE_K(32)>;
label = "ITCM";
};

dtcm: memory@20000000 {
compatible = "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(32)>;
label = "DTCM";
};

bram0: memory@60000000 {
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1 change: 1 addition & 0 deletions boards/arm/mps2_an521/mps2_an521.dts
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sram1: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 DT_SIZE_M(4)>;
label = "SRAM1";
};

sram2_3: memory@38000000 {
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1 change: 1 addition & 0 deletions boards/arm/mps2_an521/mps2_an521_nonsecure.dts
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Expand Up @@ -82,6 +82,7 @@
sram1: memory@0 {
compatible = "mmio-sram";
reg = <0x0 DT_SIZE_M(4)>;
label = "SRAM1";
};

sram2_3: memory@28000000 {
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1 change: 1 addition & 0 deletions boards/arm/mps2_an521/mps2_an521_remote.dts
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sram1: memory@0 {
compatible = "mmio-sram";
reg = <0x0 DT_SIZE_M(4)>;
label = "SRAM1";
};

sram2_3: memory@28000000 {
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2 changes: 2 additions & 0 deletions boards/arm/mps3_an547/mps3_an547.dts
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Expand Up @@ -109,6 +109,7 @@
*/
itcm: itcm@10000000 { /* alias @ 0x0 */
reg = <0x10000000 DT_SIZE_K(512)>;
label = "ITCM";
};

sram: sram@11000000 { /* alias @ 0x01000000 */
Expand All @@ -118,6 +119,7 @@

dtcm: dtcm@30000000 { /* alias @ 0x20000000 */
reg = <0x30000000 DT_SIZE_K(512)>;
label = "DTCM";
};

isram: sram@31000000 {/* alias @ 0x21000000 */
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1 change: 1 addition & 0 deletions boards/shields/v2c_daplink/v2c_daplink_cfg.overlay
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Expand Up @@ -20,6 +20,7 @@
itcm: memory@10000000 {
compatible = "arm,itcm";
reg = <0x10000000 DT_SIZE_K(64)>;
label = "ITCM";
};
};
};
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1 change: 1 addition & 0 deletions dts/arm/atmel/sam4l.dtsi
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Expand Up @@ -48,6 +48,7 @@
sram1: memory@21000000 {
compatible = "mmio-sram";
reg = <0x21000000 DT_SIZE_K(4)>;
label = "SRAM1";
};

soc {
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2 changes: 2 additions & 0 deletions dts/arm/cypress/psoc6.dtsi
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sram1: memory@8023000 {
compatible = "mmio-sram";
reg = <0x08023000 DT_SIZE_K(4)>;
label = "SRAM1";
};

sram2: memory@8024000 {
compatible = "mmio-sram";
reg = <0x08024000 DT_SIZE_K(112)>;
label = "SRAM2";
};

soc {
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1 change: 1 addition & 0 deletions dts/arm/nordic/nrf5340_cpuapp.dtsi
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Expand Up @@ -38,6 +38,7 @@

sram1: memory@21000000 {
compatible = "mmio-sram";
label = "SRAM1";
};

peripheral@50000000 {
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1 change: 1 addition & 0 deletions dts/arm/nordic/nrf5340_cpuappns.dtsi
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Expand Up @@ -39,6 +39,7 @@

sram1: memory@21000000 {
compatible = "mmio-sram";
label = "SRAM1";
};

peripheral@40000000 {
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1 change: 1 addition & 0 deletions dts/arm/nordic/nrf5340_cpunet.dtsi
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sram1: memory@21000000 {
compatible = "mmio-sram";
label = "SRAM1";
};

clock: clock@41005000 {
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2 changes: 2 additions & 0 deletions dts/arm/nxp/nxp_lpc11u6x.dtsi
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sram1:memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 0x800>;
label = "SRAM1";
};

sram2:memory@20004000 {
compatible = "mmio-sram";
reg = <0x20004000 0x800>;
label = "SRAM2";
};

soc {
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2 changes: 2 additions & 0 deletions dts/arm/nxp/nxp_lpc54xxx.dtsi
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sram1:memory@20010000 {
compatible = "mmio-sram";
reg = <0x20010000 DT_SIZE_K(64)>;
label = "SRAM1";
};

sram2:memory@20020000 {
compatible = "mmio-sram";
reg = <0x20020000 DT_SIZE_K(32)>;
label = "SRAM2";
};

sramx:memory@4000000{
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3 changes: 3 additions & 0 deletions dts/arm/nxp/nxp_lpc55S1x_common.dtsi
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sram1: memory@20008000 {
compatible = "mmio-sram";
reg = <0x20008000 DT_SIZE_K(16)>;
label = "SRAM1";
};

sram2: memory@2000c000 {
compatible = "mmio-sram";
reg = <0x2000c000 DT_SIZE_K(16)>;
label = "SRAM2";
};

sram4: memory@20010000 {
/* Conencted to USB bus*/
compatible = "mmio-sram";
reg = <0x20010000 DT_SIZE_K(16)>;
label = "SRAM4";
};
};

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3 changes: 3 additions & 0 deletions dts/arm/nxp/nxp_lpc55S2x_common.dtsi
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sram1: memory@20010000 {
compatible = "mmio-sram";
reg = <0x20010000 DT_SIZE_K(64)>;
label = "SRAM1";
};

sram2: memory@20020000 {
compatible = "mmio-sram";
reg = <0x20020000 DT_SIZE_K(64)>;
label = "SRAM2";
};

sram4: memory@20040000 {
compatible = "mmio-sram";
reg = <0x20040000 DT_SIZE_K(16)>;
label = "SRAM4";
};
};

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4 changes: 4 additions & 0 deletions dts/arm/nxp/nxp_lpc55S6x_common.dtsi
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Expand Up @@ -59,21 +59,25 @@
sram1: memory@20010000 {
compatible = "mmio-sram";
reg = <0x20010000 DT_SIZE_K(64)>;
label = "SRAM1";
};

sram2: memory@20020000 {
compatible = "mmio-sram";
reg = <0x20020000 DT_SIZE_K(64)>;
label = "SRAM2";
};

sram3: memory@20030000 {
compatible = "mmio-sram";
reg = <0x20030000 DT_SIZE_K(64)>;
label = "SRAM3";
};

sram4: memory@20040000 {
compatible = "mmio-sram";
reg = <0x20040000 DT_SIZE_K(16)>;
label = "SRAM4";
};
};

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2 changes: 2 additions & 0 deletions dts/arm/nxp/nxp_rt.dtsi
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itcm: itcm@0 {
compatible = "nxp,imx-itcm";
reg = <0x00000000 DT_SIZE_K(128)>;
label = "ITCM";
};

dtcm: dtcm@20000000 {
compatible = "nxp,imx-dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
label = "DTCM";
};

ocram: ocram@20200000 {
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1 change: 1 addition & 0 deletions dts/arm/st/f7/stm32f723.dtsi
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dtcm: memory@20000000 {
compatible = "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(64)>;
label = "DTCM";
};

soc {
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1 change: 1 addition & 0 deletions dts/arm/st/f7/stm32f745.dtsi
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dtcm: memory@20000000 {
compatible = "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(64)>;
label = "DTCM";
};

soc {
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1 change: 1 addition & 0 deletions dts/arm/st/f7/stm32f767.dtsi
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dtcm: memory@20000000 {
compatible = "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
label = "DTCM";
};

soc {
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1 change: 1 addition & 0 deletions dts/arm/st/h7/stm32h723.dtsi
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dtcm: memory@20000000 {
compatible = "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
label = "DTCM";
};

/* AXI SRAM in D1 domain (AXI bus) */
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5 changes: 5 additions & 0 deletions dts/arm/st/h7/stm32h743.dtsi
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Expand Up @@ -44,29 +44,34 @@
sram1: memory@30000000 {
reg = <0x30000000 DT_SIZE_K(128)>;
compatible = "mmio-sram";
label = "SRAM1";
};

/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
sram2: memory@30020000 {
compatible = "mmio-sram";
reg = <0x30020000 DT_SIZE_K(128)>;
label = "SRAM2";
};

/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
sram3: memory@30040000 {
compatible = "mmio-sram";
reg = <0x30040000 DT_SIZE_K(32)>;
label = "SRAM3";
};

/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
sram4: memory@38000000 {
reg = <0x38000000 DT_SIZE_K(64)>;
compatible = "mmio-sram";
label = "SRAM4";
};

dtcm: memory@20000000 {
compatible = "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
label = "DTCM";
};

otghs_fs_phy: otghs_fs_phy {
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4 changes: 4 additions & 0 deletions dts/arm/st/h7/stm32h745.dtsi
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sram1: memory@30000000 {
reg = <0x30000000 DT_SIZE_K(128)>;
compatible = "mmio-sram";
label = "SRAM1";
};

/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
sram2: memory@30020000 {
compatible = "mmio-sram";
reg = <0x30020000 DT_SIZE_K(128)>;
label = "SRAM2";
};

/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
sram3: memory@30040000 {
compatible = "mmio-sram";
reg = <0x30040000 DT_SIZE_K(32)>;
label = "SRAM3";
};

/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
sram4: memory@38000000 {
reg = <0x38000000 DT_SIZE_K(64)>;
compatible = "mmio-sram";
label = "SRAM4";
};
};
1 change: 1 addition & 0 deletions dts/arm/st/h7/stm32h745Xi_m7.dtsi
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dtcm: memory@20000000 {
compatible = "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
label = "DTCM";
};

soc {
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5 changes: 5 additions & 0 deletions dts/arm/st/h7/stm32h750.dtsi
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Expand Up @@ -23,28 +23,33 @@
sram1: memory@30000000 {
reg = <0x30000000 DT_SIZE_K(128)>;
compatible = "mmio-sram";
label = "SRAM1";
};

/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
sram2: memory@30020000 {
compatible = "mmio-sram";
reg = <0x30020000 DT_SIZE_K(128)>;
label = "SRAM2";
};

/* System data RAM accessible over AHB bus: SRAM3 in D2 domain */
sram3: memory@30040000 {
compatible = "mmio-sram";
reg = <0x30040000 DT_SIZE_K(32)>;
label = "SRAM3";
};

/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
sram4: memory@38000000 {
reg = <0x38000000 DT_SIZE_K(64)>;
compatible = "mmio-sram";
label = "SRAM4";
};

dtcm: memory@20000000 {
compatible = "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
label = "DTCM";
};
};
2 changes: 2 additions & 0 deletions dts/arm/st/wb/stm32wb.dtsi
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Expand Up @@ -35,11 +35,13 @@
sram1: memory@20030000 {
compatible = "mmio-sram";
reg = <0x20030000 0x2800>;
label = "SRAM1";
};

sram2: memory@20038000 {
compatible = "mmio-sram";
reg = <0x20038000 0x5000>;
label = "SRAM2";
};

clocks {
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2 changes: 1 addition & 1 deletion dts/arm/ti/cc1352r.dtsi
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Expand Up @@ -22,7 +22,7 @@

/* CCFG registers occupy the last 88 bytes of flash */
ti_ccfg_partition: partition@57fa8 {
label = "ti_ccfg";
label = "FLASH_CCFG";
reg = <0x57fa8 88>;
};
};
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1 change: 1 addition & 0 deletions dts/arm/ti/cc13x2_cc26x2.dtsi
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sram1: memory@11000000 {
compatible = "mmio-sram";
reg = <0x11000000 0x2000>;
label = "SRAM1";
};

flash0: serial-flash@0 {
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