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Merged
merged 6 commits into from
Aug 17, 2021
Merged

Add disk driver support for RT600 #37625

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08eb3b3
dts: rt6xx: Add GPIO 2
mmahadevan108 Aug 6, 2021
d8bbe5e
drivers: lpc_gpio: Fix warning when interrupt is not defined
mmahadevan108 Aug 6, 2021
9ab2820
drivers: clock_control: Update LPC clock driver for USDHC
mmahadevan108 Jul 27, 2021
5c1a3c1
drivers: disk: Update NXP USDHC driver
mmahadevan108 Aug 6, 2021
82bd0ba
mxrt685: Add USDHC support for RT685
mmahadevan108 Aug 11, 2021
008f86b
soc: mxrt: Replace duplicate use of usdhc1
mmahadevan108 Aug 17, 2021
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3 changes: 3 additions & 0 deletions boards/arm/mimxrt685_evk/Kconfig.defconfig
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Expand Up @@ -38,4 +38,7 @@ config HEAP_MEM_POOL_SIZE

endif # DMA_MCUX_LPC

config DISK_DRIVER_SDMMC
default y if DISK_DRIVERS

endif # BOARD_MIMXRT685_EVK
20 changes: 20 additions & 0 deletions boards/arm/mimxrt685_evk/doc/index.rst
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Expand Up @@ -91,6 +91,8 @@ features:
+-----------+------------+-------------------------------------+
| WDT | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| SDHC | on-chip | disk access |
+-----------+------------+-------------------------------------+

The default configuration can be found in the defconfig file:

Expand Down Expand Up @@ -165,6 +167,24 @@ functionality of a pin.
+---------+-----------------+----------------------------+
| PIO0_27 | SCT0_OUT7 | PWM |
+---------+-----------------+----------------------------+
| PIO1_30 | SD0_CLK | SD card |
+---------+-----------------+----------------------------+
| PIO1_31 | SD0_CMD | SD card |
+---------+-----------------+----------------------------+
| PIO2_0 | SD0_D0 | SD card |
+---------+-----------------+----------------------------+
| PIO2_1 | SD0_D1 | SD card |
+---------+-----------------+----------------------------+
| PIO2_2 | SD0_D2 | SD card |
+---------+-----------------+----------------------------+
| PIO2_3 | SD0_D3 | SD card |
+---------+-----------------+----------------------------+
| PIO2_4 | SD0_WR_PRT | SD card |
+---------+-----------------+----------------------------+
| PIO2_9 | SD0_CD | SD card |
+---------+-----------------+----------------------------+
| PIO2_10 | SD0_RST | SD card |
+---------+-----------------+----------------------------+

System Clock
============
Expand Down
9 changes: 9 additions & 0 deletions boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts
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Expand Up @@ -253,6 +253,10 @@ i2s1: &flexcomm3 {
status = "okay";
};

&gpio2 {
status = "okay";
};

&dma0 {
/*
* The total number of dma channels available is defined by
Expand Down Expand Up @@ -293,3 +297,8 @@ i2s1: &flexcomm3 {
&sc_timer {
status = "okay";
};

&usdhc1 {
status = "okay";
pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
};
1 change: 1 addition & 0 deletions boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml
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Expand Up @@ -25,5 +25,6 @@ supported:
- hwinfo
- i2c
- i2s
- sdhc
- spi
- watchdog
191 changes: 191 additions & 0 deletions boards/arm/mimxrt685_evk/pinmux.c
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Expand Up @@ -768,6 +768,197 @@ static int mimxrt685_evk_pinmux_init(const struct device *dev)
IOPCTL_PinMuxSet(IOPCTL, 0U, 31U, port0_pin31_config);
#endif

#endif

#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
uint32_t port1_pin30_config = (/* Pin is configured as SD0_CLK */
IOPCTL_PIO_FUNC1 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT1 PIN30 (coords: P10) is configured as SD0_CLK */
IOPCTL_PinMuxSet(IOPCTL, 1U, 30U, port1_pin30_config);

uint32_t port1_pin31_config = (/* Pin is configured as SD0_CMD */
IOPCTL_PIO_FUNC1 |
/* Enable pull-up / pull-down function */
IOPCTL_PIO_PUPD_EN |
/* Enable pull-up function */
IOPCTL_PIO_PULLUP_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT1 PIN31 (coords: R9) is configured as SD0_CMD */
IOPCTL_PinMuxSet(IOPCTL, 1U, 31U, port1_pin31_config);

uint32_t port2_pin0_config = (/* Pin is configured as SD0_D0 */
IOPCTL_PIO_FUNC1 |
/* Enable pull-up / pull-down function */
IOPCTL_PIO_PUPD_EN |
/* Enable pull-up function */
IOPCTL_PIO_PULLUP_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT2 PIN0 (coords: R11) is configured as SD0_D0 */
IOPCTL_PinMuxSet(IOPCTL, 2U, 0U, port2_pin0_config);

uint32_t port2_pin1_config = (/* Pin is configured as SD0_D1 */
IOPCTL_PIO_FUNC1 |
/* Enable pull-up / pull-down function */
IOPCTL_PIO_PUPD_EN |
/* Enable pull-up function */
IOPCTL_PIO_PULLUP_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT2 PIN1 (coords: T11) is configured as SD0_D1 */
IOPCTL_PinMuxSet(IOPCTL, 2U, 1U, port2_pin1_config);

uint32_t port2_pin10_config = (/* Pin is configured as PIO2_10 */
IOPCTL_PIO_FUNC0 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Disable input buffer function */
IOPCTL_PIO_INBUF_DI |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT2 PIN10 (coords: T15) is configured as PIO2_10 */
IOPCTL_PinMuxSet(IOPCTL, 2U, 10U, port2_pin10_config);

uint32_t port2_pin2_config = (/* Pin is configured as SD0_D2 */
IOPCTL_PIO_FUNC1 |
/* Enable pull-up / pull-down function */
IOPCTL_PIO_PUPD_EN |
/* Enable pull-up function */
IOPCTL_PIO_PULLUP_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT2 PIN2 (coords: U11) is configured as SD0_D2 */
IOPCTL_PinMuxSet(IOPCTL, 2U, 2U, port2_pin2_config);

uint32_t port2_pin3_config = (/* Pin is configured as SD0_D3 */
IOPCTL_PIO_FUNC1 |
/* Enable pull-up / pull-down function */
IOPCTL_PIO_PUPD_EN |
/* Enable pull-up function */
IOPCTL_PIO_PULLUP_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT2 PIN3 (coords: T12) is configured as SD0_D3 */
IOPCTL_PinMuxSet(IOPCTL, 2U, 3U, port2_pin3_config);

uint32_t port2_pin4_config = (/* Pin is configured as PIO2_4 */
IOPCTL_PIO_FUNC0 |
/* Disable pull-up / pull-down function */
IOPCTL_PIO_PUPD_DI |
/* Enable pull-down function */
IOPCTL_PIO_PULLDOWN_EN |
/* Disable input buffer function */
IOPCTL_PIO_INBUF_DI |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT2 PIN4 (coords: T13) is configured as PIO2_4 */
IOPCTL_PinMuxSet(IOPCTL, 2U, 4U, port2_pin4_config);

uint32_t port2_pin9_config = (/* Pin is configured as SD0_CARD_DET_N */
IOPCTL_PIO_FUNC1 |
/* Enable pull-up / pull-down function */
IOPCTL_PIO_PUPD_EN |
/* Enable pull-up function */
IOPCTL_PIO_PULLUP_EN |
/* Enables input buffer function */
IOPCTL_PIO_INBUF_EN |
/* Normal mode */
IOPCTL_PIO_SLEW_RATE_NORMAL |
/* Normal drive */
IOPCTL_PIO_FULLDRIVE_DI |
/* Analog mux is disabled */
IOPCTL_PIO_ANAMUX_DI |
/* Pseudo Output Drain is disabled */
IOPCTL_PIO_PSEDRAIN_DI |
/* Input function is not inverted */
IOPCTL_PIO_INV_DI);
/* PORT2 PIN9 (coords: R13) is configured as SD0_CARD_DET_N */
IOPCTL_PinMuxSet(IOPCTL, 2U, 9U, port2_pin9_config);
#endif

return 0;
Expand Down
8 changes: 8 additions & 0 deletions drivers/clock_control/clock_control_mcux_syscon.c
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Expand Up @@ -72,6 +72,14 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(
LOG_ERR("Missing feature define for HS_SPI clock!");
#endif
break;
#if (defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT)
case MCUX_USDHC1_CLK:
*rate = CLOCK_GetSdioClkFreq(0);
break;
case MCUX_USDHC2_CLK:
*rate = CLOCK_GetSdioClkFreq(1);
break;
#endif
}
#endif

Expand Down
58 changes: 32 additions & 26 deletions drivers/disk/usdhc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2256,7 +2256,6 @@ static void usdhc_host_reset(struct usdhc_priv *priv)
usdhc_enable_ddr_mode(base, false, 0);
usdhc_tuning(base, SDHC_STANDARD_TUNING_START, SDHC_TUINIG_STEP, false);
#if FSL_FEATURE_USDHC_HAS_HS400_MODE
#error Not implemented!
/* Disable HS400 mode */
/* Disable DLL */
#endif
Expand Down Expand Up @@ -2600,8 +2599,9 @@ static K_MUTEX_DEFINE(z_usdhc_init_lock);
static int usdhc_board_access_init(struct usdhc_priv *priv)
{
const struct usdhc_config *config = priv->config;
int ret;
int ret = 0;
uint32_t gpio_level;
USDHC_Type *base = config->base;

if (config->pwr_name) {
priv->pwr_gpio = device_get_binding(config->pwr_name);
Expand Down Expand Up @@ -2634,35 +2634,41 @@ static int usdhc_board_access_init(struct usdhc_priv *priv)
}

if (!priv->detect_gpio) {
LOG_INF("USDHC detection other than GPIO not implemented!");
return 0;
}
LOG_INF("USDHC detection other than GPIO");
/* DATA3 does not monitor card insertion */
base->PROT_CTRL &= ~USDHC_PROT_CTRL_D3CD_MASK;
if ((base->PRES_STATE & USDHC_PRES_STATE_CINST_MASK) != 0) {
priv->inserted = true;
} else {
priv->inserted = false;
ret = -ENODEV;
}
} else {
ret = usdhc_cd_gpio_init(priv->detect_gpio,
config->detect_pin,
config->detect_flags,
&priv->detect_cb);
if (ret) {
return ret;
}
ret = gpio_pin_get(priv->detect_gpio, config->detect_pin);
if (ret < 0) {
return ret;
}

ret = usdhc_cd_gpio_init(priv->detect_gpio,
config->detect_pin,
config->detect_flags,
&priv->detect_cb);
if (ret) {
return ret;
}
ret = gpio_pin_get(priv->detect_gpio, config->detect_pin);
if (ret < 0) {
return ret;
}
gpio_level = ret;

gpio_level = ret;
if (gpio_level == 0) {
priv->inserted = false;
LOG_ERR("NO SD inserted!");

if (gpio_level == 0) {
priv->inserted = false;
LOG_ERR("NO SD inserted!");
return -ENODEV;
}

return -ENODEV;
priv->inserted = true;
LOG_INF("SD inserted!");
}

priv->inserted = true;
LOG_INF("SD inserted!");

return 0;
return ret;
}

static int usdhc_access_init(const struct device *dev)
Expand Down
4 changes: 2 additions & 2 deletions drivers/gpio/gpio_mcux_lpc.c
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Expand Up @@ -364,6 +364,7 @@ static const clock_ip_name_t gpio_clock_names[] = GPIO_CLOCKS;

#define GPIO_MCUX_LPC_IRQ_CONNECT(n, m) \
do { \
struct gpio_mcux_lpc_data *data = dev->data; \
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, m, irq), \
DT_INST_IRQ_BY_IDX(n, m, priority), \
gpio_mcux_lpc_port_isr, DEVICE_DT_INST_GET(n), 0); \
Expand All @@ -374,6 +375,7 @@ static const clock_ip_name_t gpio_clock_names[] = GPIO_CLOCKS;
#define GPIO_MCUX_LPC_IRQ(n, m) \
COND_CODE_1(DT_INST_IRQ_HAS_IDX(n, m), (GPIO_MCUX_LPC_IRQ_CONNECT(n, m)), ())


#define GPIO_MCUX_LPC(n) \
static int lpc_gpio_init_##n(const struct device *dev); \
\
Expand All @@ -398,8 +400,6 @@ static const clock_ip_name_t gpio_clock_names[] = GPIO_CLOCKS;
\
static int lpc_gpio_init_##n(const struct device *dev) \
{ \
struct gpio_mcux_lpc_data *data = dev->data; \
\
gpio_mcux_lpc_init(dev); \
\
GPIO_MCUX_LPC_IRQ(n, 0); \
Expand Down
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