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tests: arch: arm_thread_swap: Fix FPSCR validation for ARMv8.1-M #37908

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Merged
merged 3 commits into from
Aug 25, 2021
Merged

tests: arch: arm_thread_swap: Fix FPSCR validation for ARMv8.1-M #37908

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ed938cd
tests: arch: arm_thread_swap: Fix FPSCR validation for ARMv8.1-M
stephanosio Aug 24, 2021
f5f49a1
tests: arch: arm_no_multithreading: Fix FPSCR validation for ARMv8.1-M
stephanosio Aug 24, 2021
c503f74
tests: arch: arm_no_multithreading: Run on mps3_an547 board
stephanosio Aug 24, 2021
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12 changes: 11 additions & 1 deletion tests/arch/arm/arm_no_multithreading/src/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,16 @@
#error test can only run on Cortex-M MCUs
#endif

#if defined(CONFIG_ARMV8_1_M_MAINLINE)
/*
* For ARMv8.1-M, the FPSCR[18:16] LTPSIZE field may always read 0b010 if MVE
* is not implemented, so mask it when validating the value of the FPSCR.
*/
#define FPSCR_MASK (~FPU_FPDSCR_LTPSIZE_Msk)
#else
#define FPSCR_MASK (0xffffffffU)
#endif

extern K_THREAD_STACK_DEFINE(z_main_stack, CONFIG_MAIN_STACK_SIZE);

static volatile int test_flag;
Expand Down Expand Up @@ -58,7 +68,7 @@ void test_main(void)
psp, main_stack_base, main_stack_top);

#if defined(CONFIG_FPU)
__ASSERT(__get_FPSCR() == 0,
__ASSERT((__get_FPSCR() & FPSCR_MASK) == 0,
"FPSCR not zero (0x%x)", __get_FPSCR());
#endif

Expand Down
2 changes: 1 addition & 1 deletion tests/arch/arm/arm_no_multithreading/testcase.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -6,4 +6,4 @@ tests:
arch.arm.no_multithreading:
filter: not CONFIG_TRUSTED_EXECUTION_NONSECURE
platform_allow: qemu_cortex_m0 qemu_cortex_m3 mps2_an385 mps2_an521
nrf52840dk_nrf52840 nrf9160dk_nrf9160 nrf51dk_nrf51422
mps3_an547 nrf52840dk_nrf52840 nrf9160dk_nrf9160 nrf51dk_nrf51422
14 changes: 12 additions & 2 deletions tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c
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Expand Up @@ -30,6 +30,16 @@
#define EXC_RETURN_FTYPE (0x00000010UL)
#endif

#if defined(CONFIG_ARMV8_1_M_MAINLINE)
/*
* For ARMv8.1-M, the FPSCR[18:16] LTPSIZE field may always read 0b010 if MVE
* is not implemented, so mask it when validating the value of the FPSCR.
*/
#define FPSCR_MASK (~FPU_FPDSCR_LTPSIZE_Msk)
#else
#define FPSCR_MASK (0xffffffffU)
#endif

extern void z_move_thread_to_end_of_prio_q(struct k_thread *thread);

static struct k_thread alt_thread;
Expand Down Expand Up @@ -278,7 +288,7 @@ static void alt_thread_entry(void)


/* Verify that the _current_ (alt) thread is initialized with FPSCR cleared. */
zassert_true(__get_FPSCR() == 0,
zassert_true((__get_FPSCR() & FPSCR_MASK) == 0,
"(Alt thread) FPSCR is not cleared at initialization: 0x%x\n", __get_FPSCR());

zassert_true((p_ztest_thread->arch.mode_exc_return & EXC_RETURN_FTYPE) == 0,
Expand Down Expand Up @@ -461,7 +471,7 @@ void test_arm_thread_swap(void)
"CONTROL.FPCA is not cleared at initialization: 0x%x\n",
__get_CONTROL());
/* Verify that the main test thread is initialized with FPSCR cleared. */
zassert_true(__get_FPSCR() == 0,
zassert_true((__get_FPSCR() & FPSCR_MASK) == 0,
"FPSCR is not cleared at initialization: 0x%x\n", __get_FPSCR());

/* Clear the thread's floating-point callee-saved registers' container.
Expand Down