b_u585i_iot02a: Enable I2C, HTS221 sensor and stop modes

boards/arm/b_u585i_iot02a/Kconfig.defconfig

@@ -12,4 +12,9 @@ config SPI_STM32_INTERRUPT
 	default y
 	depends on SPI
 
+choice STM32_LPTIM_CLOCK
+	default STM32_LPTIM_CLOCK_LSE
+	depends on STM32_LPTIM_TIMER
+endchoice
+
 endif # BOARD_B_U585I_IOT02A

boards/arm/b_u585i_iot02a/arduino_r3_connector.dtsi

@@ -36,3 +36,4 @@
 };
 
 arduino_spi: &spi1 {};
+arduino_i2c: &i2c1 {};

boards/arm/b_u585i_iot02a/b_u585i_iot02a-common.dtsi

@@ -28,6 +28,27 @@
 			gpios = <&gpioc 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
 		};
 	};
+
+	power-states {
+		stop0: state0 {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			substate-id = <1>;
+			min-residency-us = <100>;
+		};
+		stop1: state1 {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			substate-id = <2>;
+			min-residency-us = <500>;
+		};
+		stop2: state2 {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			substate-id = <3>;
+			min-residency-us = <900>;
+		};
+	};
 };
 
 &clk_lse {

boards/arm/b_u585i_iot02a/b_u585i_iot02a.dts

@@ -25,6 +25,14 @@
 	};
 };
 
+&cpu0 {
+	cpu-power-states = <&stop0 &stop1 &stop2>;
+};
+
+&lptim1 {
+	status = "okay";
+};
+
 &usart1 {
 	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
 	current-speed = <115200>;
@@ -36,3 +44,21 @@
 		     &spi1_miso_pe14 &spi1_mosi_pe15>;
 	status = "okay";
 };
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_scl_ph4 &i2c2_sda_ph5>;
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	hts221@5f {
+		compatible = "st,hts221";
+		reg = <0x5f>;
+		label = "HTS221";
+	};
+};

boards/arm/b_u585i_iot02a/b_u585i_iot02a.yaml

@@ -9,5 +9,7 @@ toolchain:
 ram: 786
 flash: 2048
 supported:
+  - arduino_i2c
   - arduino_spi
+  - hts221
   - spi

boards/arm/b_u585i_iot02a/doc/index.rst

@@ -175,10 +175,11 @@ The Zephyr b_u585i_iot02a board configuration supports the following hardware fe
 +-----------+------------+-------------------------------------+
 | GPIO      | on-chip    | gpio                                |
 +-----------+------------+-------------------------------------+
+| I2C       | on-chip    | i2c                                 |
++-----------+------------+-------------------------------------+
 | SPI       | on-chip    | spi                                 |
 +-----------+------------+-------------------------------------+
 
-
 The default configuration can be found in the defconfig file:
 
 	``boards/arm/b_u585i_iot02a/b_u585i_iot02a_defconfig``
@@ -200,6 +201,8 @@ Default Zephyr Peripheral Mapping:
 - LD2 : PH6
 - user button : PC13
 - SPI1 NSS/SCK/MISO/MOSI : PE12/P13/P14/P15 (Arduino SPI)
+- I2C_1 SDA/SDL : PB9/PB8 (Arduino I2C)
+- I2C_2 SDA/SDL : PH5/PH4
 
 System Clock
 ------------

drivers/clock_control/clock_stm32_ll_u5.c

@@ -324,6 +324,10 @@ void config_src_sysclk_pll(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
 				     STM32_PLL_N_MULTIPLIER,
 				     STM32_PLL_R_DIVISOR);
 
+	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
+	while (LL_PWR_IsActiveFlag_VOS() == 0) {
+	}
+
 	if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= 55) {
 		/*
 		 * Set EPOD prescaler based on PLL1 input freq (MSI/PLLM)

drivers/timer/stm32_lptim_timer.c

@@ -83,8 +83,13 @@ int sys_clock_driver_init(const struct device *dev)
 	ARG_UNUSED(dev);
 
 	/* enable LPTIM clock source */
+#if defined(LL_APB1_GRP1_PERIPH_LPTIM1)
 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1);
 	LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
+#elif defined(LL_APB3_GRP1_PERIPH_LPTIM1)
+	LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_LPTIM1);
+	LL_SRDAMR_GRP1_EnableAutonomousClock(LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN);
+#endif
 
 #if defined(CONFIG_STM32_LPTIM_CLOCK_LSI)
 	/* enable LSI clock */
@@ -137,28 +142,51 @@ int sys_clock_driver_init(const struct device *dev)
 	LL_LPTIM_SetClockSource(LPTIM1, LL_LPTIM_CLK_SOURCE_INTERNAL);
 	/* configure the LPTIM1 prescaler with 1 */
 	LL_LPTIM_SetPrescaler(LPTIM1, LL_LPTIM_PRESCALER_DIV1);
+#ifdef CONFIG_SOC_SERIES_STM32U5X
+	LL_LPTIM_OC_SetPolarity(LPTIM1, LL_LPTIM_CHANNEL_CH1,
+				LL_LPTIM_OUTPUT_POLARITY_REGULAR);
+#else
 	LL_LPTIM_SetPolarity(LPTIM1, LL_LPTIM_OUTPUT_POLARITY_REGULAR);
+#endif
 	LL_LPTIM_SetUpdateMode(LPTIM1, LL_LPTIM_UPDATE_MODE_IMMEDIATE);
 	LL_LPTIM_SetCounterMode(LPTIM1, LL_LPTIM_COUNTER_MODE_INTERNAL);
 	LL_LPTIM_DisableTimeout(LPTIM1);
 	/* counting start is initiated by software */
 	LL_LPTIM_TrigSw(LPTIM1);
 
+#ifdef CONFIG_SOC_SERIES_STM32U5X
+	/* Enable the LPTIM1 before proceeding with configuration */
+	LL_LPTIM_Enable(LPTIM1);
+
+	LL_LPTIM_DisableIT_CC1(LPTIM1);
+	while (LL_LPTIM_IsActiveFlag_DIEROK(LPTIM1) == 0) {
+	}
+	LL_LPTIM_ClearFlag_DIEROK(LPTIM1);
+	LL_LPTIM_ClearFLAG_CC1(LPTIM1);
+#else
 	/* LPTIM1 interrupt set-up before enabling */
 	/* no Compare match Interrupt */
 	LL_LPTIM_DisableIT_CMPM(LPTIM1);
 	LL_LPTIM_ClearFLAG_CMPM(LPTIM1);
+#endif
 
 	/* Autoreload match Interrupt */
 	LL_LPTIM_EnableIT_ARRM(LPTIM1);
+#ifdef CONFIG_SOC_SERIES_STM32U5X
+	while (LL_LPTIM_IsActiveFlag_DIEROK(LPTIM1) == 0) {
+	}
+	LL_LPTIM_ClearFlag_DIEROK(LPTIM1);
+#endif
 	LL_LPTIM_ClearFLAG_ARRM(LPTIM1);
 	/* ARROK bit validates the write operation to ARR register */
 	LL_LPTIM_ClearFlag_ARROK(LPTIM1);
 
 	accumulated_lptim_cnt = 0;
 
+#ifndef CONFIG_SOC_SERIES_STM32U5X
 	/* Enable the LPTIM1 counter */
 	LL_LPTIM_Enable(LPTIM1);
+#endif
 
 	/* Set the Autoreload value once the timer is enabled */
 	if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
@@ -175,7 +203,12 @@ int sys_clock_driver_init(const struct device *dev)
 
 #ifdef CONFIG_DEBUG
 	/* stop LPTIM1 during DEBUG */
+#if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
 	LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP);
+#elif defined(LL_DBGMCU_APB3_GRP1_LPTIM1_STOP)
+	LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_APB3_GRP1_LPTIM1_STOP);
+#endif
+
 #endif
 	return 0;
 }
@@ -210,14 +243,24 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
 
 	if (ticks == K_TICKS_FOREVER) {
 		/* disable LPTIM clock to avoid counting */
+#if defined(LL_APB1_GRP1_PERIPH_LPTIM1)
 		LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1);
+#elif defined(LL_APB3_GRP1_PERIPH_LPTIM1)
+		LL_APB3_GRP1_DisableClock(LL_APB3_GRP1_PERIPH_LPTIM1);
+#endif
 		return;
 	}
 
 	/* if LPTIM clock was previously stopped, it must now be restored */
+#if defined(LL_APB1_GRP1_PERIPH_LPTIM1)
 	if (!LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1)) {
 		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1);
 	}
+#elif defined(LL_APB3_GRP1_PERIPH_LPTIM1)
+	if (!LL_APB3_GRP1_IsEnabledClock(LL_APB3_GRP1_PERIPH_LPTIM1)) {
+		LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_LPTIM1);
+	}
+#endif
 
 	/* passing ticks==1 means "announce the next tick",
 	 * ticks value of zero (or even negative) is legal and

dts/arm/st/u5/stm32u5.dtsi

@@ -8,6 +8,7 @@
 #include <arm/armv8-m.dtsi>
 #include <dt-bindings/clock/stm32_clock.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
 #include <freq.h>
 
 / {
@@ -280,6 +281,44 @@
 			status = "disabled";
 			label = "SPI_3";
 		};
+
+		i2c1: i2c@40005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			interrupts = <55 0>, <56 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_1";
+		};
+
+		i2c2: i2c@40005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005800 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			interrupts = <57 0>, <58 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+			label= "I2C_2";
+		};
+
+		lptim1: timers@46004400 {
+			compatible = "st,stm32-lptim";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x46004400 0x400>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>;
+			interrupts = <67 1>;
+			interrupt-names = "wakeup";
+			status = "disabled";
+			label = "LPTIM_1";
+		};
 	};
 };
 

soc/arm/st_stm32/stm32u5/CMakeLists.txt

@@ -4,3 +4,7 @@ zephyr_include_directories(${ZEPHYR_BASE}/drivers)
 zephyr_sources(
   soc.c
   )
+
+zephyr_sources_ifdef(CONFIG_PM
+  power.c
+  )

soc/arm/st_stm32/stm32u5/Kconfig.defconfig.series

@@ -10,4 +10,7 @@ source "soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5*"
 config SOC_SERIES
 	default "stm32u5"
 
+config STM32_LPTIM_TIMER
+	default y if PM
+
 endif # SOC_SERIES_STM32U5X