Introduce GD32F4xx serial SoCs with GD32F450i_EVAL board

boards/arm/gd32f450i_eval/CMakeLists.txt

@@ -0,0 +1,5 @@
+# Copyright (c) 2021, ATL Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_sources(board.c)

boards/arm/gd32f450i_eval/Kconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2021 ATL-Electronics
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INIT_PRIORITY
+	int "Board initialization priority"
+	default 50
+	help
+	  Board initialization priority.

boards/arm/gd32f450i_eval/Kconfig.board

@@ -0,0 +1,6 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_GD32F450I_EVAL
+	bool "GigaDevice GD32F450I Evaluation Kit"
+	depends on SOC_GD32F450I

boards/arm/gd32f450i_eval/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_GD32F450I_EVAL
+
+config BOARD
+	default "gd32f450i_eval"
+
+endif # BOARD_GD32F450I_EVAL

boards/arm/gd32f450i_eval/board.c

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <init.h>
+
+#include <gd32f4xx.h>
+
+/** Initialize the board's hardware through GD32 HAL */
+static int board_init(const struct device *dev)
+{
+	/* Enable GPIOA clock for PA9, PA10 */
+	rcu_periph_clock_enable(RCU_GPIOA);
+
+	/* Pin AF definition can be found in datasheet Device overview section */
+	gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_9);
+	gpio_af_set(GPIOA, GPIO_AF_7, GPIO_PIN_10);
+
+	/* Configure USART0 Tx as alternate function push-pull */
+	gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_9);
+	gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
+
+	/* Configure USART0 Rx as alternate function push-pull */
+	gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_10);
+	gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_10);
+
+	return 0;
+}
+
+SYS_INIT(board_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);

boards/arm/gd32f450i_eval/board.cmake

@@ -0,0 +1,10 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=GD32F450IK")
+board_runner_args(jlink "--iface=JTAG")
+board_runner_args(jlink "--speed=4000")
+board_runner_args(jlink "--tool-opt=-jtagconf -1,-1")
+board_runner_args(jlink "--tool-opt=-autoconnect 1")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/arm/gd32f450i_eval/gd32f450i_eval.dts

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <gigadevice/gd32f450ikh6.dtsi>
+
+/ {
+	model = "GigaDevice GD32F450I Evaluation Kit";
+	compatible = "gd,gd32f450i";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &usart0;
+		zephyr,shell-uart = &usart0;
+	};
+};
+
+&usart0 {
+	status = "okay";
+
+	current-speed = <115200>;
+};

boards/arm/gd32f450i_eval/gd32f450i_eval.yaml

@@ -0,0 +1,13 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: gd32f450i_eval
+name: GigaDevice GD32F450I Evaluation Kit
+type: mcu
+arch: arm
+ram: 256
+flash: 3072
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools

boards/arm/gd32f450i_eval/gd32f450i_eval_defconfig

@@ -0,0 +1,14 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_GD32F4=y
+CONFIG_SOC_GD32F450I=y
+CONFIG_BOARD_GD32F450I_EVAL=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_CORTEX_M_SYSTICK=y
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y

dts/arm/gigadevice/gd32f405.dtsi

@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+				arm,num-mpu-regions = <8>;
+			};
+		};
+	};
+
+	soc {
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+		};
+
+		fmc: flash-controller@40023c00 {
+			compatible = "gd,gd32-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40023c00 0x400>;
+			peripheral-id = <6>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH_0";
+			};
+		};
+
+		usart0: usart@40011000 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40011000 0x400>;
+			interrupts = <37 0>;
+			rcu-periph-clock = <0x1104>;
+			status = "disabled";
+			label = "usart_0";
+		};
+
+		usart1: usart@40004400 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40004400 0x400>;
+			interrupts = <38 0>;
+			rcu-periph-clock = <0x1011>;
+			status = "disabled";
+			label = "usart_1";
+		};
+
+		usart2: usart@40004800 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40004800 0x400>;
+			interrupts = <39 0>;
+			rcu-periph-clock = <0x1012>;
+			status = "disabled";
+			label = "usart_2";
+		};
+
+		uart3: usart@40004c00 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40004c00 0x400>;
+			interrupts = <52 0>;
+			rcu-periph-clock = <0x1013>;
+			status = "disabled";
+			label = "uart_3";
+		};
+
+		uart4: usart@40005000 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40005000 0x400>;
+			interrupts = <52 0>;
+			rcu-periph-clock = <0x1014>;
+			status = "disabled";
+			label = "uart_4";
+		};
+
+		usart5: usart@40011400 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40011400 0x400>;
+			interrupts = <71 0>;
+			rcu-periph-clock = <0x1105>;
+			status = "disabled";
+			label = "usart_5";
+		};
+
+		uart6: usart@40007800 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40007800 0x400>;
+			interrupts = <82 0>;
+			rcu-periph-clock = <0x101e>;
+			status = "disabled";
+			label = "uart_6";
+		};
+
+		uart7: usart@40007c00 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40007c00 0x400>;
+			interrupts = <83 0>;
+			rcu-periph-clock = <0x101f>;
+			status = "disabled";
+			label = "uart_7";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};

dts/arm/gigadevice/gd32f405vgt6.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <gigadevice/gd32f405.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(192)>;
+		};
+	};
+};

dts/arm/gigadevice/gd32f407.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <gigadevice/gd32f405.dtsi>

dts/arm/gigadevice/gd32f450.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <gigadevice/gd32f405.dtsi>

dts/arm/gigadevice/gd32f450ikh6.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <gigadevice/gd32f450.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(3072)>;
+			};
+		};
+
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(256)>;
+		};
+	};
+};

modules/hal_gigadevice/CMakeLists.txt

@@ -5,12 +5,27 @@ if(CONFIG_HAS_GD32_HAL)
 
 zephyr_library_named(hal_gigadevice)
 
-if(CONFIG_SOC_SERIES_GD32F403)
-  set(gd32_soc_uc GD32F403)
-  set(gd32_soc_lc gd32f403)
+if(CONFIG_SOC_SERIES_GD32F4)
+  if(CONFIG_SOC_SERIES_GD32F403)
+    set(gd32_soc_df GD32F403)
+    set(gd32_soc_uc GD32F403)
+    set(gd32_soc_lc gd32f403)
+  elseif(CONFIG_SOC_SERIES_GD32F405)
+    set(gd32_soc_df GD32F405)
+    set(gd32_soc_uc GD32F4XX)
+    set(gd32_soc_lc gd32f4xx)
+  elseif(CONFIG_SOC_SERIES_GD32F407)
+    set(gd32_soc_df GD32F407)
+    set(gd32_soc_uc GD32F4XX)
+    set(gd32_soc_lc gd32f4xx)
+  elseif(CONFIG_SOC_SERIES_GD32F450)
+    set(gd32_soc_df GD32F450)
+    set(gd32_soc_uc GD32F4XX)
+    set(gd32_soc_lc gd32f4xx)
+  endif()
 endif()
 
-zephyr_library_compile_definitions(${gd32_soc_uc})
+zephyr_compile_definitions(${gd32_soc_df})
 
 set(gd32_soc_dir     ${ZEPHYR_HAL_GIGADEVICE_MODULE_DIR}/${gd32_soc_uc})
 set(gd32_cmsis_dir   ${gd32_soc_dir}/CMSIS/GD/${gd32_soc_uc})
@@ -30,20 +45,27 @@ zephyr_library_sources_ifdef(CONFIG_USE_GD32_CRC   ${gd32_std_src_dir}/${gd32_so
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_CTC   ${gd32_std_src_dir}/${gd32_soc_lc}_ctc.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_DAC   ${gd32_std_src_dir}/${gd32_soc_lc}_dac.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_DBG   ${gd32_std_src_dir}/${gd32_soc_lc}_dbg.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_DCI   ${gd32_std_src_dir}/${gd32_soc_lc}_dci.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_DMA   ${gd32_std_src_dir}/${gd32_soc_lc}_dma.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_ENET  ${gd32_std_src_dir}/${gd32_soc_lc}_enet.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_EXMC  ${gd32_std_src_dir}/${gd32_soc_lc}_exmc.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_EXTI  ${gd32_std_src_dir}/${gd32_soc_lc}_exti.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_FMC   ${gd32_std_src_dir}/${gd32_soc_lc}_fmc.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_FWDGT ${gd32_std_src_dir}/${gd32_soc_lc}_fwdgt.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_GPIO  ${gd32_std_src_dir}/${gd32_soc_lc}_gpio.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_I2C   ${gd32_std_src_dir}/${gd32_soc_lc}_i2c.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_IPA   ${gd32_std_src_dir}/${gd32_soc_lc}_ipa.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_IREF  ${gd32_std_src_dir}/${gd32_soc_lc}_iref.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_MISC  ${gd32_std_src_dir}/${gd32_soc_lc}_misc.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_PMU   ${gd32_std_src_dir}/${gd32_soc_lc}_pmu.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_RCU   ${gd32_std_src_dir}/${gd32_soc_lc}_rcu.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_RTC   ${gd32_std_src_dir}/${gd32_soc_lc}_rtc.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_SDIO  ${gd32_std_src_dir}/${gd32_soc_lc}_sdio.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_SPI   ${gd32_std_src_dir}/${gd32_soc_lc}_spi.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_SYSCFG ${gd32_std_src_dir}/${gd32_soc_lc}_syscfg.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_TIMER ${gd32_std_src_dir}/${gd32_soc_lc}_timer.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_TLI   ${gd32_std_src_dir}/${gd32_soc_lc}_tli.c)
+zephyr_library_sources_ifdef(CONFIG_USE_GD32_TRNG  ${gd32_std_src_dir}/${gd32_soc_lc}_trng.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_USART ${gd32_std_src_dir}/${gd32_soc_lc}_usart.c)
 zephyr_library_sources_ifdef(CONFIG_USE_GD32_WWDGT ${gd32_std_src_dir}/${gd32_soc_lc}_wwdgt.c)