pinctrl: initial support for GD32

boards/arm/gd32f403z_eval/gd32f403z_eval-pinctrl.dtsi

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021, Teslabs Engineering S.L.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/gd32f403z(k-i-g-e-c-b)xx-pinctrl.h>
+
+&pinctrl {
+	usart0_default: usart0_default {
+		group1 {
+			pinmux = <USART0_TX_PA9_NORMP>, <USART0_RX_PA10_NORMP>;
+		};
+	};
+};

boards/arm/gd32f403z_eval/gd32f403z_eval.dts

@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include <gigadevice/gd32f403/gd32f403zet6.dtsi>
+#include "gd32f403z_eval-pinctrl.dtsi"
 
 / {
 	model = "GigaDevice GD32F403Z Evaluation Kit";
@@ -21,6 +22,7 @@
 
 &usart0 {
 	status = "okay";
-
 	current-speed = <115200>;
+	pinctrl-0 = <&usart0_default>;
+	pinctrl-names = "default";
 };

boards/arm/gd32f450i_eval/gd32f450i_eval-pinctrl.dtsi

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021, Teslabs Engineering S.L.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
+
+&pinctrl {
+	usart0_default: usart0_default {
+		group1 {
+			pinmux = <USART0_TX_PA9>, <USART0_RX_PA10>;
+		};
+	};
+};

boards/arm/gd32f450i_eval/gd32f450i_eval.dts

@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include <gigadevice/gd32f4xx/gd32f450ik.dtsi>
+#include "gd32f450i_eval-pinctrl.dtsi"
 
 / {
 	model = "GigaDevice GD32F450I-EVAL";
@@ -22,4 +23,6 @@
 &usart0 {
 	status = "okay";
 	current-speed = <115200>;
+	pinctrl-0 = <&usart0_default>;
+	pinctrl-names = "default";
 };

drivers/pinctrl/CMakeLists.txt

@@ -3,3 +3,5 @@
 
 zephyr_library()
 zephyr_library_sources(common.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AF pinctrl_gd32_af.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c)

drivers/pinctrl/Kconfig

@@ -29,4 +29,6 @@ config PINCTRL_DYNAMIC
 	  runtime. This can be useful, for example, to change the pins assigned to a
 	  peripheral at early boot stages depending on a certain input.
 
+source "drivers/pinctrl/Kconfig.gd32"
+
 endif # PINCTRL

drivers/pinctrl/Kconfig.gd32

@@ -0,0 +1,21 @@
+# Copyright (c) 2021 Teslabs Engineering S.L.
+# SPDX-License-Identifier: Apache-2.0
+
+DT_COMPAT_GIGADEVICE_GD32_PINCTRL_AF := gd,gd32-pinctrl-af
+DT_COMPAT_GIGADEVICE_GD32_PINCTRL_AFIO := gd,gd32-pinctrl-afio
+
+config PINCTRL_GD32_AF
+	bool "GD32 AF pin controller driver"
+	depends on SOC_FAMILY_GD32 && GD32_HAS_AF_PINMUX
+	default $(dt_compat_enabled,$(DT_COMPAT_GIGADEVICE_GD32_PINCTRL_AF))
+	help
+	  GD32 AF pin controller driver. This driver is used by series using the
+	  AF pin multiplexing model.
+
+config PINCTRL_GD32_AFIO
+	bool "GD32 AFIO pin controller driver"
+	depends on SOC_FAMILY_GD32 && GD32_HAS_AFIO_PINMUX
+	default $(dt_compat_enabled,$(DT_COMPAT_GIGADEVICE_GD32_PINCTRL_AFIO))
+	help
+	  GD32 AFIO pin controller driver. This driver is used by series using the
+	  AFIO pin multiplexing model.

drivers/pinctrl/pinctrl_gd32_af.c

@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2021 Teslabs Engineering S.L.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <drivers/pinctrl.h>
+
+BUILD_ASSERT((GD32_PUPD_NONE == GPIO_PUPD_NONE) &&
+	     (GD32_PUPD_PULLUP == GPIO_PUPD_PULLUP) &&
+	     (GD32_PUPD_PULLDOWN == GPIO_PUPD_PULLDOWN),
+	     "pinctrl pull-up/down definitions != HAL definitions");
+
+BUILD_ASSERT((GD32_OTYPE_PP == GPIO_OTYPE_PP) &&
+	     (GD32_OTYPE_OD == GPIO_OTYPE_OD),
+	     "pinctrl output type definitions != HAL definitions");
+
+BUILD_ASSERT((GD32_OSPEED_2MHZ == GPIO_OSPEED_2MHZ) &&
+	     (GD32_OSPEED_25MHZ == GPIO_OSPEED_25MHZ) &&
+	     (GD32_OSPEED_50MHZ == GPIO_OSPEED_50MHZ) &&
+	     (GD32_OSPEED_200MHZ == GPIO_OSPEED_200MHZ),
+	     "pinctrl output speed definitions != HAL definitions");
+
+/** Utility macro that expands to the GPIO port address if it exists */
+#define GD32_PORT_ADDR_OR_NONE(nodelabel)				       \
+	COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)),		       \
+		   (DT_REG_ADDR(DT_NODELABEL(nodelabel)),), ())
+
+/** Utility macro that expands to the GPIO RCU if it exists */
+#define GD32_PORT_RCU_OR_NONE(nodelabel)				       \
+	COND_CODE_1(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)),		       \
+		   (DT_PROP(DT_NODELABEL(nodelabel), rcu_periph_clock),), ())
+
+/** GD32 port addresses */
+static const uint32_t gd32_port_addrs[] = {
+	GD32_PORT_ADDR_OR_NONE(gpioa)
+	GD32_PORT_ADDR_OR_NONE(gpiob)
+	GD32_PORT_ADDR_OR_NONE(gpioc)
+	GD32_PORT_ADDR_OR_NONE(gpiod)
+	GD32_PORT_ADDR_OR_NONE(gpioe)
+	GD32_PORT_ADDR_OR_NONE(gpiof)
+	GD32_PORT_ADDR_OR_NONE(gpiog)
+	GD32_PORT_ADDR_OR_NONE(gpioh)
+	GD32_PORT_ADDR_OR_NONE(gpioi)
+};
+
+/** GD32 port RCUs */
+static const uint32_t gd32_port_rcus[] = {
+	GD32_PORT_RCU_OR_NONE(gpioa)
+	GD32_PORT_RCU_OR_NONE(gpiob)
+	GD32_PORT_RCU_OR_NONE(gpioc)
+	GD32_PORT_RCU_OR_NONE(gpiod)
+	GD32_PORT_RCU_OR_NONE(gpioe)
+	GD32_PORT_RCU_OR_NONE(gpiof)
+	GD32_PORT_RCU_OR_NONE(gpiog)
+	GD32_PORT_RCU_OR_NONE(gpioh)
+	GD32_PORT_RCU_OR_NONE(gpioi)
+};
+
+/**
+ * @brief Configure a pin.
+ *
+ * @param pin The pin to configure.
+ */
+static void pinctrl_configure_pin(pinctrl_soc_pin_t pin)
+{
+	uint8_t port_idx;
+	uint32_t rcu, port, pin_num, af, mode;
+
+	port_idx = GD32_PORT_GET(pin);
+	__ASSERT_NO_MSG(port_idx < ARRAY_SIZE(gd32_port_addrs));
+
+	rcu = gd32_port_rcus[port_idx];
+	port = gd32_port_addrs[port_idx];
+	pin_num = BIT(GD32_PIN_GET(pin));
+	af = GD32_AF_GET(pin);
+
+	rcu_periph_clock_enable(rcu);
+
+	if (af != GD32_ANALOG) {
+		mode = GPIO_MODE_AF;
+		gpio_af_set(port, af, pin_num);
+	} else {
+		mode = GPIO_MODE_ANALOG;
+	}
+
+	gpio_mode_set(port, mode, GD32_PUPD_GET(pin), pin_num);
+	gpio_output_options_set(port, GD32_OTYPE_GET(pin),
+				GD32_OSPEED_GET(pin), pin_num);
+
+	rcu_periph_clock_disable(rcu);
+}
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
+			   uintptr_t reg)
+{
+	ARG_UNUSED(reg);
+
+	for (uint8_t i = 0U; i < pin_cnt; i++) {
+		pinctrl_configure_pin(pins[i]);
+	}
+
+	return 0;
+}