[POC | RFC | DNM] Introducing framework to configure MPU regions from DT-defined SRAM regions

samples/memory/sram_regions/CMakeLists.txt

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(sram_mpu)
+
+target_sources(app PRIVATE src/main.c src/arm_mpu_regions.c)

samples/memory/sram_regions/boards/dt_mpu_attr.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2021 Carlo Caione <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifdef __DTS__
+
+#define DT_256B		(0x07U)
+#define DT_512B		(0x08U)
+#define DT_1KB		(0x09U)
+#define DT_2KB		(0x0aU)
+#define DT_4KB		(0x0bU)
+#define DT_8KB		(0x0cU)
+#define DT_16KB		(0x0dU)
+#define DT_32KB		(0x0eU)
+#define DT_64KB		(0x0fU)
+#define DT_128KB	(0x10U)
+#define DT_256KB	(0x11U)
+#define DT_512KB	(0x12U)
+#define DT_1MB		(0x13U)
+#define DT_2MB		(0x14U)
+#define DT_4MB		(0x15U)
+#define DT_8MB		(0x16U)
+#define DT_16MB		(0x17U)
+#define DT_32MB		(0x18U)
+#define DT_64MB		(0x19U)
+#define DT_128MB	(0x1aU)
+#define DT_256MB	(0x1bU)
+#define DT_512MB	(0x1cU)
+#define DT_1GB		(0x1dU)
+#define DT_2GB		(0x1eU)
+#define DT_4GB		(0x1fU)
+
+/*
+ * NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE |
+ * MPU_RASR_XN_Msk | P_RW_U_NA_Msk
+ */
+#define DT_SRAM_ATTR(size) (0x110b0000 | size)
+
+/*
+ * NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE |
+ * MPU_RASR_XN_Msk | P_RW_U_NA_Msk
+ */
+#define DT_SRAM_NOCACHE_ATTR(size) (0x11080000 | size)
+
+#endif /* __DTS__ */

samples/memory/sram_regions/boards/mps2_an385.overlay

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2021 Carlo Caione <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "dt_mpu_attr.h"
+
+/ {
+	/delete-node/ memory@20000000;
+
+	chosen {
+		zephyr,sram-no-cache = &sram_no_cache;
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+		reg = <0x20000000 0x200000>;
+	};
+
+	sram_attr_0: memory@20200000 {
+		compatible = "mmio-sram";
+		reg = <0x20200000 0x100000>;
+		mpu-attr = <DT_SRAM_ATTR(DT_1MB)>;
+		label = "region0";
+	};
+
+	sram_no_cache: memory@20300000 {
+		compatible = "mmio-sram";
+		reg = <0x20300000 0x100000>;
+		mpu-attr = <DT_SRAM_NOCACHE_ATTR(DT_1MB)>;
+		label = "region1";
+	};
+};

samples/memory/sram_regions/linker_sram_regions.ld

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) Carlo Caione <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <autoconf.h>
+#include <linker/sections.h>
+#include <devicetree.h>
+
+#include <linker/linker-defs.h>
+#include <linker/linker-tool.h>
+
+#include <linker/devicetree_sram.h>
+
+MEMORY
+{
+	LINKER_DT_SRAM_REGIONS()
+}
+
+SECTIONS
+{
+	LINKER_DT_SRAM_SECTIONS()
+}
+
+#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

samples/memory/sram_regions/prj.conf

@@ -0,0 +1,3 @@
+CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS=y
+CONFIG_HAVE_CUSTOM_LINKER_SCRIPT=y
+CONFIG_CUSTOM_LINKER_SCRIPT="linker_sram_regions.ld"

samples/memory/sram_regions/sample.yaml

@@ -0,0 +1,8 @@
+sample:
+  description: SRAM MPU sample application
+  name: sram_mpu
+tests:
+  sample.memory.sram_regions:
+    platform_allow: mps2_an385
+    tags: sample board sram mpu
+    build_only: true

samples/memory/sram_regions/src/arm_mpu_regions.c

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2021 Carlo Caione <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <sys/slist.h>
+#include <arch/arm/aarch32/mpu/arm_mpu.h>
+#include <linker/devicetree_sram.h>
+
+#define BUILD_MPU_REGION(p_name, p_base, p_size, p_attr)	\
+	{ .name = p_name,					\
+	  .base = p_base,					\
+	  .attr.rasr = p_attr,					\
+	},
+
+static const struct arm_mpu_region mpu_regions[] = {
+	/* FLASH */
+	MPU_REGION_ENTRY("FLASH_0",
+			 CONFIG_FLASH_BASE_ADDRESS,
+			 REGION_FLASH_ATTR(REGION_4M)),
+
+	/* SRAM0 */
+	MPU_REGION_ENTRY("SRAM_0",
+			 CONFIG_SRAM_BASE_ADDRESS,
+			 REGION_RAM_ATTR(REGION_2M)),
+
+	/* Generated SRAM regions */
+	DT_SRAM_INST_FOREACH(BUILD_MPU_REGION)
+};
+
+const struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};

samples/memory/sram_regions/src/main.c

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 Carlo Caione <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+#include <linker/linker-defs.h>
+#include <linker/devicetree_sram.h>
+
+uint32_t var_in_region0 __attribute((__section__("region0"))) = 0xaabbccdd;
+uint32_t var_in_region1 __attribute((__section__("region1"))) = 0xddccbbaa;
+
+uint32_t buf_in_nocache[0xA] __nocache_sram;
+
+void main(void)
+{
+	printk("Address of var_in_region0: %p\n", &var_in_region0);
+	printk("Address of var_in_region1: %p\n", &var_in_region1);
+
+	printk("Address of buf_in_nocache: %p\n", buf_in_nocache);
+}