pinctrl: mcux_rt1xxx: add pinctrl support for rt1xxx series

boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi_defconfig

@@ -13,3 +13,4 @@ CONFIG_SERIAL=y
 CONFIG_GPIO=y
 CONFIG_ARM_MPU=y
 CONFIG_HW_STACK_PROTECTION=y
+CONFIG_PINMUX=y

boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2021, NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/mcux_rt-pinctrl.h>
+
+&pinctrl {
+	sai1_default: sai1_default {
+		IOMUXC_GPIO_AD_B1_09_SAI1_MCLK {
+			pinmux = <0x401F8120 0x3 0x401F858C 0x1 0x401F8310>;
+			nxp,mcux_input;
+			nxp,mcux_dse = <6>;
+			nxp,mcux_speed = <2>;
+			nxp,mcux_pke;
+		};
+		IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 {
+			pinmux = <0x401F812C 0x3 0x401F8594 0x1 0x401F831C>;
+			nxp,mcux_input;
+			nxp,mcux_dse = <6>;
+			nxp,mcux_speed = <2>;
+			nxp,mcux_pke;
+		};
+		IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 {
+			pinmux = <0x401F8130 0x3 0 0 0x401F8320>;
+			nxp,mcux_input;
+			nxp,mcux_dse = <6>;
+			nxp,mcux_speed = <2>;
+			nxp,mcux_pke;
+		};
+		IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK {
+			pinmux = <0x401F8134 0x3 0x401F85A8 0x1 0x401F8324>;
+			nxp,mcux_input;
+			nxp,mcux_dse = <6>;
+			nxp,mcux_speed = <2>;
+			nxp,mcux_pke;
+		};
+		IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC {
+			pinmux = <0x401F8138 0x3 0x401F85AC 0x1 0x401F8328>;
+			nxp,mcux_input;
+			nxp,mcux_dse = <6>;
+			nxp,mcux_speed = <2>;
+			nxp,mcux_pke;
+		};
+	};
+	lpuart1_default: lpuart1_default {
+		IOMUXC_GPIO_AD_B0_12_LPUART1_TX {
+			pinmux = <0x401F80EC 0x2 0 0 0x401F82DC>;
+			nxp,mcux_speed = <2>;
+			nxp,mcux_dse = <6>;
+			nxp,mcux_pke;
+		};
+		IOMUXC_GPIO_AD_B0_13_LPUART1_RX {
+			pinmux = <0x401F80F0 0x2 0 0 0x401F82E0>;
+			nxp,mcux_speed = <2>;
+			nxp,mcux_dse = <6>;
+			nxp,mcux_pke;
+		};
+	};
+	status = "okay";
+};

boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts

@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include <nxp/nxp_rt1060.dtsi>
+#include "mimxrt1060_evk-pinctrl.dtsi"
 
 / {
 	model = "NXP MIMXRT1060-EVK board";
@@ -164,6 +165,8 @@ arduino_serial: &lpuart3 {};
 &lpuart1 {
 	status = "okay";
 	current-speed = <115200>;
+	pinctrl-0 = <&lpuart1_default>;
+	pinctrl-names = "default";
 };
 
 &enet {
@@ -218,6 +221,8 @@ zephyr_udc0: &usb1 {
 
 &sai1 {
 	status = "okay";
+	pinctrl-0 = <&sai1_default>;
+	pinctrl-names = "default";
 };
 
 /* Enable GPT for use as a hardware timer. This disables Cortex Systick.
@@ -226,3 +231,7 @@ zephyr_udc0: &usb1 {
 &gpt_hw_timer {
 	status = "okay";
 };
+
+&iomuxcgpr {
+	status = "okay";
+};

boards/arm/mimxrt1060_evk/pinmux.c

@@ -114,22 +114,6 @@ static int mimxrt1060_evk_init(const struct device *dev)
 	IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0);
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL
-	/* LPUART1 TX/RX */
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0);
-
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX,
-			    IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
-			    IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
-			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
-
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX,
-			    IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
-			    IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
-			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
-#endif
-
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart3), okay) && CONFIG_SERIAL
 	/* LPUART3 TX/RX */
 	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0);
@@ -388,20 +372,6 @@ static int mimxrt1060_evk_init(const struct device *dev)
 			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(sai1), okay) && CONFIG_I2S
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 1U);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 1U);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 1U);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 1U);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 1U);
-
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 0x10B0u);
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 0x10B0u);
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 0x10B0u);
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 0x10B0u);
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 0x10B0u);
-#endif
-
 	return 0;
 }
 

drivers/i2s/i2s_mcux_sai.c

@@ -16,8 +16,8 @@
 #include <device.h>
 #include <init.h>
 #include <drivers/dma.h>
-
 #include <drivers/i2s.h>
+#include <drivers/pinctrl.h>
 #include <drivers/clock_control.h>
 #include <dt-bindings/clock/imx_ccm.h>
 #include <soc.h>
@@ -78,6 +78,7 @@ struct i2s_mcux_config {
 	uint32_t tx_channel;
 	clock_control_subsys_t clk_sub_sys;
 	const struct device *ccm_dev;
+	const struct pinctrl_dev_config *pinctrl;
 	void (*irq_connect)(const struct device *dev);
 	bool rx_sync_mode;
 	bool tx_sync_mode;
@@ -328,15 +329,25 @@ static void enable_mclk_direction(const struct device *dev, bool dir)
 	const struct i2s_mcux_config *dev_cfg = dev->config;
 	uint32_t offset = dev_cfg->mclk_pin_offset;
 	uint32_t mask = dev_cfg->mclk_pin_mask;
-	uint32_t value = 0;
 	uint32_t *gpr =  (uint32_t *)DT_REG_ADDR(DT_NODELABEL(iomuxcgpr)) + offset;
 
 	if (dir) {
 		*gpr |= mask;
 	} else {
 		*gpr &= ~mask;
 	}
+}
+
+static void mcux_rt_sai_pin_init(void)
+{
+	int err;
+	uint8_t state = 0;
 
+	err = pinctrl_apply_state(dev_cfg->pinctrl, state);
+	if (err < 0) {
+		LOG_ERR("mclk pinctrl setup failed (%d)", err);
+		return err;
+	}
 }
 
 static void get_mclk_rate(const struct device *dev, uint32_t *mclk)
@@ -1034,6 +1045,9 @@ static int i2s_mcux_initialize(const struct device *dev)
 	/* register ISR */
 	dev_cfg->irq_connect(dev);
 
+	/* pinctrl */
+	mcux_rt_sai_pin_init();
+
 	/*clock configuration*/
 	audio_clock_settings(dev);
 
@@ -1085,6 +1099,8 @@ static const struct i2s_driver_api i2s_mcux_driver_api = {
 #define I2S_MCUX_INIT(i2s_id)						\
 	static void i2s_irq_connect_##i2s_id(const struct device *dev); \
 									\
+	PINCTRL_DT_INST_DEFINE(i2s_id)					\
+									\
 	static const struct i2s_mcux_config i2s_##i2s_id##_config = {	\
 		.base = (I2S_Type *)DT_INST_REG_ADDR(i2s_id),		\
 		.clk_src =						\
@@ -1116,6 +1132,7 @@ static const struct i2s_driver_api i2s_mcux_driver_api = {
 		.clk_sub_sys =	(clock_control_subsys_t)		\
 			DT_INST_CLOCKS_CELL_BY_IDX(i2s_id, 0, name),	\
 		.ccm_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(i2s_id)),	\
+		.pinctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(i2s_id),	\
 		.irq_connect = i2s_irq_connect_##i2s_id,		\
 		.tx_sync_mode =						\
 			   DT_INST_PROP(i2s_id, nxp_tx_sync_mode),	\

drivers/pinctrl/CMakeLists.txt

@@ -7,3 +7,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AF pinctrl_gd32_af.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_NRF pinctrl_nrf.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCUX_RT pinctrl_mcux_rt.c)

drivers/pinctrl/Kconfig

@@ -32,5 +32,6 @@ config PINCTRL_DYNAMIC
 source "drivers/pinctrl/Kconfig.gd32"
 source "drivers/pinctrl/Kconfig.nrf"
 source "drivers/pinctrl/Kconfig.stm32"
+source "drivers/pinctrl/Kconfig.mcux"
 
 endif # PINCTRL

drivers/pinctrl/Kconfig.mcux

@@ -0,0 +1,9 @@
+# Copyright (c) 2021 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_MCUX_RT
+	bool "Pin controller driver for MCUX RT1xxx MCUs"
+	depends on SOC_SERIES_IMX_RT
+	default y
+	help
+	  Enable pin controller driver for NXP RT series MCUs

drivers/pinctrl/pinctrl_mcux_rt.c

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <drivers/pinctrl.h>
+#include <soc.h>
+#include <fsl_iomuxc.h>
+#include <fsl_gpio.h>
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
+			   uintptr_t reg)
+{
+	uint8_t i;
+
+	/* configure all pins */
+	for (i = 0U; i < pin_cnt; i++) {
+		uint32_t mux_register = pins[i].pinmux.mux_register;
+		uint32_t mux_mode = pins[i].pinmux.mux_mode;
+		uint32_t input_register = pins[i].pinmux.input_register;
+		uint32_t input_daisy = pins[i].pinmux.input_daisy;
+		uint32_t config_register = pins[i].pinmux.config_register;
+		uint32_t input_on_field = pins[i].pinmux.input_on_field;
+		uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags;
+
+		IOMUXC_SetPinMux(mux_register, mux_mode, input_register,
+			input_daisy, config_register, input_on_field);
+		IOMUXC_SetPinConfig(mux_register, mux_mode, input_register,
+			input_daisy, config_register, pin_ctrl_flags);
+	}
+
+	return 0;
+}
+
+static int mcux_pinctrl_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	CLOCK_EnableClock(kCLOCK_Iomuxc);
+	CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+
+	return 0;
+}
+
+SYS_INIT(mcux_pinctrl_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

drivers/serial/uart_mcux_lpuart.c

@@ -13,10 +13,16 @@
 #include <device.h>
 #include <drivers/uart.h>
 #include <drivers/clock_control.h>
+#ifdef CONFIG_PINCTRL
+#include <drivers/pinctrl.h>
+#endif
 
 struct mcux_lpuart_config {
 	LPUART_Type *base;
 	const struct device *clock_dev;
+#ifdef CONFIG_PINCTRL
+	const struct pinctrl_dev_config *pinctrl;
+#endif
 	clock_control_subsys_t clock_subsys;
 	uint32_t baud_rate;
 	uint8_t flow_ctrl;
@@ -353,6 +359,10 @@ static int mcux_lpuart_init(const struct device *dev)
 	const struct mcux_lpuart_config *config = dev->config;
 	struct mcux_lpuart_data *data = dev->data;
 	struct uart_config *uart_api_config = &data->uart_config;
+#ifdef CONFIG_PINCTRL
+	int err;
+	uint8_t state = 0;
+#endif
 
 	uart_api_config->baudrate = config->baud_rate;
 	uart_api_config->parity = UART_CFG_PARITY_NONE;
@@ -362,6 +372,12 @@ static int mcux_lpuart_init(const struct device *dev)
 
 	/* set initial configuration */
 	mcux_lpuart_configure_init(dev, uart_api_config);
+#ifdef CONFIG_PINCTRL
+	err = pinctrl_apply_state(config->pinctrl, state);
+	if (err < 0) {
+		return err;
+	}
+#endif
 
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	config->irq_config_func(dev);
@@ -425,10 +441,13 @@ static const struct uart_driver_api mcux_lpuart_driver_api = {
 	LPUART_MCUX_DECLARE_CFG(n, LPUART_MCUX_IRQ_CFG_FUNC_INIT)
 #endif
 
+#if CONFIG_PINCTRL
+
 #define LPUART_MCUX_DECLARE_CFG(n, IRQ_FUNC_INIT)			\
 static const struct mcux_lpuart_config mcux_lpuart_##n##_config = {	\
 	.base = (LPUART_Type *) DT_INST_REG_ADDR(n),			\
 	.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),		\
+	.pinctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
 	.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
 	.baud_rate = DT_INST_PROP(n, current_speed),			\
 	.flow_ctrl = DT_INST_PROP(n, hw_flow_control) ?	\
@@ -440,6 +459,8 @@ static const struct mcux_lpuart_config mcux_lpuart_##n##_config = {	\
 									\
 	static struct mcux_lpuart_data mcux_lpuart_##n##_data;		\
 									\
+	PINCTRL_DT_INST_DEFINE(n)					\
+									\
 	static const struct mcux_lpuart_config mcux_lpuart_##n##_config;\
 									\
 	DEVICE_DT_INST_DEFINE(n,					\
@@ -456,3 +477,37 @@ static const struct mcux_lpuart_config mcux_lpuart_##n##_config = {	\
 	LPUART_MCUX_INIT_CFG(n);
 
 DT_INST_FOREACH_STATUS_OKAY(LPUART_MCUX_INIT)
+#else
+
+#define LPUART_MCUX_DECLARE_CFG(n, IRQ_FUNC_INIT)			\
+static const struct mcux_lpuart_config mcux_lpuart_##n##_config = {	\
+	.base = (LPUART_Type *) DT_INST_REG_ADDR(n),			\
+	.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),		\
+	.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
+	.baud_rate = DT_INST_PROP(n, current_speed),			\
+	.flow_ctrl = DT_INST_PROP(n, hw_flow_control) ?	\
+		UART_CFG_FLOW_CTRL_RTS_CTS : UART_CFG_FLOW_CTRL_NONE,\
+	IRQ_FUNC_INIT							\
+}
+
+#define LPUART_MCUX_INIT(n)						\
+									\
+	static struct mcux_lpuart_data mcux_lpuart_##n##_data;		\
+									\
+	static const struct mcux_lpuart_config mcux_lpuart_##n##_config;\
+									\
+	DEVICE_DT_INST_DEFINE(n,					\
+			    &mcux_lpuart_init,				\
+			    NULL,					\
+			    &mcux_lpuart_##n##_data,			\
+			    &mcux_lpuart_##n##_config,			\
+			    PRE_KERNEL_1,				\
+			    CONFIG_SERIAL_INIT_PRIORITY,		\
+			    &mcux_lpuart_driver_api);			\
+									\
+	LPUART_MCUX_CONFIG_FUNC(n)					\
+									\
+	LPUART_MCUX_INIT_CFG(n);
+
+DT_INST_FOREACH_STATUS_OKAY(LPUART_MCUX_INIT)
+#endif