Rt1170 Dual Core and OpenAMP support

boards/arm/mimxrt1160_evk/Kconfig.defconfig

@@ -11,9 +11,25 @@ config BOARD
 
 choice CODE_LOCATION
 	default CODE_FLEXSPI if BOARD_MIMXRT1160_EVK_CM7
+	default CODE_OCRAM if BOARD_MIMXRT1160_EVK_CM4 && SECOND_CORE_MCUX
 	default CODE_SRAM0 if BOARD_MIMXRT1160_EVK_CM4
 endchoice
 
+if SECOND_CORE_MCUX && BOARD_MIMXRT1160_EVK_CM4
+
+config BUILD_OUTPUT_INFO_HEADER
+	default y
+
+DT_CHOSEN_IMAGE_M4 = nxp,m4-partition
+
+# Adjust the offset of the output image if building for RT11xx SOC
+config BUILD_OUTPUT_ADJUST_LMA
+	default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \
+	$(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \
+	$(dt_node_reg_addr_hex,/soc/ocram@20200000)"
+
+endif
+
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 240000000 if BOARD_MIMXRT1160_EVK_CM4 && CORTEX_M_SYSTICK
 	default 600000000 if BOARD_MIMXRT1160_EVK_CM7 && CORTEX_M_SYSTICK

boards/arm/mimxrt1160_evk/board.cmake

@@ -4,12 +4,10 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-if(CONFIG_SOC_MIMXRT1166_CM7)
+if(CONFIG_SOC_MIMXRT1166_CM7 OR CONFIG_SECOND_CORE_MCUX)
 board_runner_args(pyocd "--target=mimxrt1160_cm7")
 board_runner_args(jlink "--device=MIMXRT1166xxx6_M7" "--reset-after-load")
-endif()
-
-if(CONFIG_SOC_MIMXRT1166_CM4)
+elseif(CONFIG_SOC_MIMXRT1166_CM4)
 board_runner_args(pyocd "--target=mimxrt1160_cm4")
 # Note: Please use JLINK above V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core)
 board_runner_args(jlink "--device=MIMXRT1166xxx6_M4")

boards/arm/mimxrt1160_evk/doc/index.rst

@@ -172,6 +172,35 @@ The MIMXRT1160 SoC has six pairs of pinmux/gpio controllers.
 | GPIO_AD_04    | FLEXPWM1_PWM2   | pwm                       |
 +---------------+-----------------+---------------------------+
 
+
+Dual Core samples
+*****************
+
++-----------+------------------+----------------------------+
+| Core      | Boot Address     | Comment                    |
++===========+==================+============================+
+| Cortex M7 | 0x30000000[630K] | primary core               |
++-----------+------------------+----------------------------+
+| Cortex M4 | 0x20020000[96k]  | boots from OCRAM           |
++-----------+------------------+----------------------------+
+
++----------+------------------+-----------------------+
+| Memory   | Address[Size]    | Comment               |
++==========+==================+=======================+
+| flexspi1 | 0x30000000[16M]  | Cortex M7 flash       |
++----------+------------------+-----------------------+
+| sdram0   | 0x80030000[64M]  | Cortex M7 ram         |
++----------+------------------+-----------------------+
+| ocram    | 0x20020000[512K] | Cortex M4 "flash"     |
++----------+------------------+-----------------------+
+| sram1    | 0x20000000[128K] | Cortex M4 ram         |
++----------+------------------+-----------------------+
+| ocram2   | 0x200C0000[512K] | Mailbox/shared memory |
++----------+------------------+-----------------------+
+
+Only the first 16K of ocram2 has the correct MPU region attributes set to be
+used as shared memory
+
 System Clock
 ============
 
@@ -190,6 +219,20 @@ Programming and Debugging
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
+Building a Dual-Core Image
+==========================
+Dual core samples load the M4 core image from flash into the shared ``ocram``
+region. The M7 core then sets the M4 boot address to this region. The only
+sample currently enabled for dual core builds is the ``openamp`` sample.
+To flash a dual core sample, the M4 image must be flashed first, so that it is
+written to flash. Then, the M7 image must be flashed. The openamp sysbuild
+sample will do this automatically by setting the image order.
+
+The secondary core can be debugged normally in single core builds
+(where the target is ``mimxrt1160_evk_cm4``). For dual core builds, the
+secondary core should be placed into a loop, then a debugger can be attached
+(see `AN13264`_, section 4.2.3 for more information)
+
 Configuring a Debug Probe
 =========================
 
@@ -285,3 +328,6 @@ should see the following message in the terminal:
 
 .. _Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK:
    https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1160-EVK-or-MIMXRT1170-EVK/ta-p/1529760
+
+.. _AN13264:
+   https://www.nxp.com/docs/en/application-note/AN13264.pdf

boards/arm/mimxrt1160_evk/mimxrt1160_evk.dtsi

@@ -81,6 +81,54 @@
 	};
 };
 
+&flexspi {
+	status = "okay";
+	ahb-prefetch;
+	ahb-read-addr-opt;
+	rx-clock-source = <1>;
+	reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>;
+	is25wp128: is25wp128@0 {
+		compatible = "nxp,imx-flexspi-nor";
+		size = <134217728>;
+		reg = <0>;
+		spi-max-frequency = <133000000>;
+		status = "okay";
+		jedec-id = [9d 70 17];
+		erase-block-size = <4096>;
+		write-block-size = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			boot_partition: partition@0 {
+				label = "mcuboot";
+				reg = <0x00000000 DT_SIZE_K(128)>;
+			};
+			/* Note slot 0 has one additional sector,
+			 * this is intended for use with the swap move algorithm
+			 */
+			slot0_partition: partition@20000 {
+				label = "image-0";
+				reg = <0x00020000 0x301000>;
+			};
+			slot1_partition: partition@321000 {
+				label = "image-1";
+				reg = <0x00321000 0x300000>;
+			};
+			scratch_partition: partition@621000 {
+				label = "image-scratch";
+				reg = <0x00621000 DT_SIZE_K(128)>;
+			};
+			storage_partition: partition@641000 {
+				label = "storage";
+				reg = <0x00641000 DT_SIZE_K(1856)>;
+			};
+		};
+	};
+};
+
 &flexpwm1_pwm2 {
 	status = "okay";
 	pinctrl-0 = <&pinmux_flexpwm1>;

boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts

@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <nxp/nxp_rt1160_cm4.dtsi>
+#include <nxp/nxp_rt11xx_cm4.dtsi>
 #include "mimxrt1160_evk.dtsi"
 
 / {
@@ -25,6 +25,8 @@
 		zephyr,shell-uart = &lpuart1;
 		zephyr,flash-controller = &is25wp128;
 		zephyr,flash = &is25wp128;
+		nxp,m4-partition = &slot1_partition;
+		zephyr,ipc = &mailbox_b;
 	};
 
 
@@ -45,52 +47,6 @@
 	status = "okay";
 };
 
-&flexspi {
-	status = "okay";
-	ahb-prefetch;
-	ahb-read-addr-opt;
-	rx-clock-source = <1>;
-	reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>;
-	is25wp128: is25wp128@0 {
-		compatible = "nxp,imx-flexspi-nor";
-		size = <134217728>;
-		reg = <0>;
-		spi-max-frequency = <133000000>;
-		status = "okay";
-		jedec-id = [9d 70 17];
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			boot_partition: partition@0 {
-				label = "mcuboot";
-				reg = <0x00000000 DT_SIZE_K(128)>;
-			};
-			/* Note slot 0 has one additional sector,
-			 * this is intended for use with the swap move algorithm
-			 */
-			slot0_partition: partition@20000 {
-				label = "image-0";
-				reg = <0x00020000 0x301000>;
-			};
-			slot1_partition: partition@321000 {
-				label = "image-1";
-				reg = <0x00321000 0x300000>;
-			};
-			scratch_partition: partition@621000 {
-				label = "image-scratch";
-				reg = <0x00621000 DT_SIZE_K(128)>;
-			};
-			storage_partition: partition@641000 {
-				label = "storage";
-				reg = <0x00641000 DT_SIZE_K(1856)>;
-			};
-		};
-	};
-};
-
 /* Enable GPT for use as a hardware timer. This disables Cortex Systick.
  * to use systick, change this node from "gpt_hw_timer" to "systick"
  */
@@ -101,3 +57,7 @@
 &edma_lpsr0 {
 	status = "okay";
 };
+
+&mailbox_b {
+	status = "okay";
+};

boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.dts

@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <nxp/nxp_rt1160_cm7.dtsi>
+#include <nxp/nxp_rt11xx_cm7.dtsi>
 #include "mimxrt1160_evk.dtsi"
 
 / {
@@ -23,6 +23,8 @@
 		zephyr,flash-controller = &is25wp128;
 		zephyr,flash = &is25wp128;
 		zephyr,code-partition = &slot0_partition;
+		zephyr,cpu1-region = &ocram;
+		zephyr,ipc = &mailbox_a;
 	};
 
 	sdram0: memory@80000000 {
@@ -58,54 +60,6 @@
 	status = "okay";
 };
 
-&flexspi {
-	status = "okay";
-	ahb-prefetch;
-	ahb-read-addr-opt;
-	rx-clock-source = <1>;
-	reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>;
-	is25wp128: is25wp128@0 {
-		compatible = "nxp,imx-flexspi-nor";
-		size = <134217728>;
-		reg = <0>;
-		spi-max-frequency = <133000000>;
-		status = "okay";
-		jedec-id = [9d 70 17];
-		erase-block-size = <4096>;
-		write-block-size = <1>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			boot_partition: partition@0 {
-				label = "mcuboot";
-				reg = <0x00000000 DT_SIZE_K(128)>;
-			};
-			/* Note slot 0 has one additional sector,
-			 * this is intended for use with the swap move algorithm
-			 */
-			slot0_partition: partition@20000 {
-				label = "image-0";
-				reg = <0x00020000 0x301000>;
-			};
-			slot1_partition: partition@321000 {
-				label = "image-1";
-				reg = <0x00321000 0x300000>;
-			};
-			scratch_partition: partition@621000 {
-				label = "image-scratch";
-				reg = <0x00621000 DT_SIZE_K(128)>;
-			};
-			storage_partition: partition@641000 {
-				label = "storage";
-				reg = <0x00641000 DT_SIZE_K(1856)>;
-			};
-		};
-	};
-};
-
 /* Enable GPT for use as a hardware timer. This disables Cortex Systick.
  * to use systick, change this node from "gpt_hw_timer" to "systick"
  */
@@ -137,3 +91,7 @@
 zephyr_udc0: &usb1 {
 	status = "okay";
 };
+
+&mailbox_a {
+	status = "okay";
+};

boards/arm/mimxrt1170_evk/Kconfig.defconfig

@@ -11,9 +11,25 @@ config BOARD
 
 choice CODE_LOCATION
 	default CODE_FLEXSPI if BOARD_MIMXRT1170_EVK_CM7
+	default CODE_OCRAM if BOARD_MIMXRT1170_EVK_CM4 && SECOND_CORE_MCUX
 	default CODE_SRAM0 if BOARD_MIMXRT1170_EVK_CM4
 endchoice
 
+if SECOND_CORE_MCUX && BOARD_MIMXRT1170_EVK_CM4
+
+config BUILD_OUTPUT_INFO_HEADER
+	default y
+
+DT_CHOSEN_IMAGE_M4 = nxp,m4-partition
+
+# Adjust the offset of the output image if building for RT11xx SOC
+config BUILD_OUTPUT_ADJUST_LMA
+	default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \
+	$(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \
+	$(dt_node_reg_addr_hex,/soc/ocram@20200000)"
+
+endif
+
 if DISK_DRIVERS
 
 config IMX_USDHC_DAT3_PWR_TOGGLE

boards/arm/mimxrt1170_evk/board.cmake

@@ -4,12 +4,10 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-if(CONFIG_SOC_MIMXRT1176_CM7)
+if(CONFIG_SOC_MIMXRT1176_CM7 OR CONFIG_SECOND_CORE_MCUX)
 board_runner_args(pyocd "--target=mimxrt1170_cm7")
 board_runner_args(jlink "--device=MIMXRT1176xxxA_M7" "--reset-after-load")
-endif()
-
-if(CONFIG_SOC_MIMXRT1176_CM4)
+elseif(CONFIG_SOC_MIMXRT1176_CM4)
 board_runner_args(pyocd "--target=mimxrt1170_cm4")
 # Note: Please use JLINK above V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core)
 board_runner_args(jlink "--device=MIMXRT1176xxxA_M4")